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FPD87352 Datenblatt(PDF) 2 Page - Texas Instruments |
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FPD87352 Datenblatt(HTML) 2 Page - Texas Instruments |
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2 / 6 page ![]() RSDS CD /12 + CLK, RSDS BUS (Back) /12 + CLK, RSDS BUS (Front) Column Start Pulse (Front) Panel Timing Controller XGA (1024 x 768) up to 95 MHz WXGA (1280 x 768) up to 95 MHz HDTV I (1280 x 720) up to 95 MHz Dot Inversion LCD panel TFT-LCD Array * Optional for 8 bit color Gray scale Reference Gray Scale Voltage Reference BUS Line Data Latch 1 n 1 n Row Start Pulse EEPROM /10 Address[9:0] /6 Memory control /32 Frame data interface /2 FPD-Link [3]* /2 FPD-Link CLK /2 FPD-Link [2] /2 FPD-Link [1] /2 FPD-Link [0] Polarity Control RSDS CD RSDS CD RSDS CD HDTV II (1366 x 768) up to 95 MHz HDTV- (1280 x 800) up to 95 MHz 2 Kb or More, 400 kHz Max /2 2-wire serial interface Panel Power Supply VDD VSS 64 Mb SDRAM 5 C OBSOLETE FPD87352 SNOSAG3C – JULY 2004 – REVISED APRIL 2013 www.ti.com System Diagram Figure 1. Block Diagram of the LCD Module 2 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: FPD87352 |
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