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M37733S4BFP Datenblatt(PDF) 10 Page - Mitsubishi Electric Semiconductor

Teilenummer M37733S4BFP
Bauteilbeschribung  16-BIT CMOS MICROCOMPUTER
PDF  36 Pages
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Hersteller  MITSUBISHI [Mitsubishi Electric Semiconductor]
Direct Link  http://www.mitsubishichips.com
Logo MITSUBISHI - Mitsubishi Electric Semiconductor

M37733S4BFP Datenblatt(HTML) 10 Page - Mitsubishi Electric Semiconductor

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MITSUBISHI MICROCOMPUTERS
M37733S4BFP
16-BIT CMOS MICROCOMPUTER
New
product
PROCESSOR MODE
The bits 0 of processor mode register 0 as shown in Figure 8 is used
to select which mode of microprocessor mode, and evaluation chip
mode.
Figure 9 shows functions of P00/A0 to P47 pins in each mode.
The external memory area also changes when the mode changes.
Figure 10 shows the memory map for each mode.
The accessing of the external memory is affected by the BYTE pin,
the bit 2 (wait bit) of processor mode register 0, and bit 0 (wait selection
bit) of processor mode register 1.
• BYTE pin
When accessing the external memory, the level of the BYTE pin is
used to determine whether to use the data bus as 8-bit width or 16-
bit width.
The data bus width is 8 bits when the level of the BYTE pin is “H”,
and P20/A16/D0 to P27/A23/D7 pins become the data I/O pins.
The data bus width is 16 bits when the level of the BYTE pin is “L”,
and both P20/A16/D0 to P27/A23/D7 pins and P10/A8/D8 to P17/A15/
D15 pins become the data I/O pins.
When accessing the internal memory, the data bus width is always
16 bits regardless of the BYTE pin level.
Fig. 8 Processor mode register bit configuration
Not used
Processor mode bit
0 : Microprocessor mode
1 : Evaluation chip mode
Wait bit
0 : Wait
1 : No Wait
Software reset bit
Reset occurs when this bit is set to “1”
Interrupt priority detection time selection bit
0 0 : Internal clock
! 7
0 1 : Internal clock
! 4
1 0 : Internal clock
! 2
This bit must be “0”
76 5 4
3 2
0
1
0
Processor mode register 0
Address
5E16
Address
5F16
Processor mode register 1
Wait selection bit
0 : Wait 0
1 : Wait 1
76 5 4
3 2
0
1
1
This bit must be “1”
(becomes “1” after reset release)



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