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UT130NHBD Datenblatt(PDF) 6 Page - Aeroflex Circuit Technology |
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UT130NHBD Datenblatt(HTML) 6 Page - Aeroflex Circuit Technology |
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6 / 8 page ![]() 6 TOOLS SUPPORTED BY AEROFLEX Aeroflex supports libraries for: • Mentor Graphics − ModelSim − Tessent FastScan - Tessent Memory • Synopsys - Design Compiler (with PowerCompiler) - PrimeTime - PrimePower - VCS for Verilog and VHDL - Formality - TetraMax • VITAL-compliant VHDL Simulation Tools • OVI-compliant Verilog Simulation Tools TRAINING AND SUPPORT Aeroflex personnel conduct training classes tailored to meet individual needs. These classes can address a wide mix of engineering backgrounds and specific customer concerns. Applications assistance is also available through all phases of ASIC Design. PHYSICAL DESIGN By using five layers of metal interconnect Aeroflex achieves optimized layouts that maximize speed of critical nets, overall chip performance and design density up to 15,000,000 equivalent gates. TEST CAPABILITY Aeroflex supports all phases of test development from test stimulus generation through high-speed production test. This support includes ATPG, fault simulation and fault grading. Scan design options are available on all UT130nHBD storage elements. Auto- matic test program development capabilities handle large vector sets for use with Aeroflex's Teradyne Tiger ATEs, supporting high-speed testing (up to 1.2GHz). QUALITY AND RELIABILITY Aeroflex is dedicated to meeting the stringent performance requirements of aerospace and defense systems suppliers. Aeroflex maintains the highest level of quality and reliability through our Quality Management Program under MIL-PRF-38535 and ISO- 9001. In 1988 we were the first gate array manufacturer to achieve QPL certification and qualification of our technology families. Our product assurance program has kept pace with the demands of certification and qualification. Our quality management plan includes the following activities and initiatives. • Quality improvement plan • Failure analysis program • SPC plan • Corrective action plan • Change control program • Standard Evaluation Circuit (SEC) and Technology Characterization Vehicle (TCV) assessment program • Certification and qualification program Because of numerous product variations permitted with customer specific designs much of the reliability testing is performed using a Standard Evaluation Circuit (SEC) and Technology Characterization Vehicle (TCV). Aeroflex utilizes the wafer foundry's data from TCV test structures to evaluate hot carrier aging, electromigration and time dependent test samples for reliability testing. |
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