Silicon Image, Inc.

Silicon Image, Inc.

7

Subject to Change without Notice

Timing Diagrams

10pF

SiI 161A

2.0 V

2.0 V

0.8 V

0.8 V

Figure 1. Digital Output Transition Times

R

CIH

R

CIL

R

CIP

2.0 V

0.8 V

0.8 V

2.0 V

2.0 V

Figure 2. Receiver Clock Cycle/High/Low Times

RX0

RX1

RX2

Figure 3. Channel-to-Channel Skew Timing

Output Timing

QE[23:0]/QO[23:0],

DE, HSYNC, VSYNC,

CTL[3:1]

ODCK_INV = 0

ODCK_INV = 1

Figure 4. Output Data, DE, and Control Signals Setup/Hold Times to ODCK Falling Edge when ODCK_INV=0, or ODCK

Rising Edge when ODCK_INV = 1.