LP5520 datasheet(22/46 Pages) TI1

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SDA

SCL

START condition

STO

P condition

SCL

SDA

data

change

allowed

data

valid

data

change

allowed

data

valid

data

change

allowed

LP5520

SNVS440B – MAY 2007 – REVISED MARCH 2016

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7.5 Programming

7.5.1 Control Interface

The LP5520 supports two different interface modes:

•

SPI interface (4-wire, serial), and

•

I2C-compatible interface (2-wire, serial)

User can define the serial interface by IF_SEL pin. IF_SEL = 0 selects the I2C mode.

7.5.1.1 I2C Compatible Interface

7.5.1.1.1

2C Signals

The serial interface is in I2C mode when IF_SEL = 0. The SCL pin is used for the I2C clock and the SDA pin is

used for bidirectional data transfer. Both these signals need a pullup resistor according to I2C specification. The

values of the pullup resistors are determined by the capacitance of the bus (typical resistance is 1.8 k

Ω). Signal

timing specifications are shown in I2C Timing Parameters .

7.5.1.1.2

2C Data Validity

The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of

the data line can only be changed when CLK is LOW.

Figure 24. I2C Signals: Data Validity

7.5.1.1.3

2C Start and Stop Conditions

START and STOP bits classify the beginning and the end of the I2C session. START condition is defined as SDA

signal transitioning from HIGH to LOW while SCL line is HIGH. STOP condition is defined as the SDA

transitioning from LOW to HIGH while SCL is HIGH. The I2C master always generates START and STOP bits.

The I2C bus is considered to be busy after START condition and free after STOP condition. During data

transmission, I2C master can generate repeated START conditions. First START and repeated START

conditions are equivalent, function-wise.

Figure 25. I2C Start and Stop Conditions

7.5.1.1.4

Transferring Data

Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.

Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated

by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver

must pull down the SDA line during the 9th clock pulse, signifying an acknowledge. A receiver which has been

addressed must generate an acknowledge after each byte has been received.

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