AD6674 datasheet(13/91 Pages) AD

13 / 91 page

Data Sheet

AD6674

Pin No.

Mnemonic

Type

Description

CMOS Outputs

17, 32

FD_A, FD_B

Output

Fast Detect Outputs for Channel A and Channel B.

Digital Inputs

20, 21

SYNCINB−,

SYNCINB+

Input

Active Low JESD204B LVDS Sync Input True/Complement.

58, 59

SYSREF+,

SYSREF−

Input

Active Low JESD204B LVDS System Reference Input True/Complement.

Data Outputs

22, 23

SERDOUT0−,

SERDOUT0+

Output

Lane 0 Output Data Complement/True.

24, 25

SERDOUT1−,

SERDOUT1+

Output

Lane 1 Output Data Complement/True.

26, 27

SERDOUT2−,

SERDOUT2+

Output

Lane 2 Output Data Complement/True.

28, 29

SERDOUT3−,

SERDOUT3+

Output

Lane 3 Output Data Complement/True.

Device Under

Test (DUT)

Controls

PDWN/STBY

Input

Power-Down Input (Active High). The operation of this pin depends on the SPI

mode and can be configured as power-down or standby.

SDIO

Input/Output

SPI Serial Data Input/Output.

SCLK

Input

SPI Serial Clock.

CSB

Input

SPI Chip Select (Active Low).

To ensure proper ADC operation, connect AVDD1_SR and AGND separately from the AVDD1 and EPAD connection. For more information, see the Applications

Information section.

Rev. B | Page 13 of 91

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