93L00 datasheet(4/8 Pages) NSC

4 / 8 page

Functional Description

The Logic Diagrams and Truth Table indicate the functional

characteristics of the 93L00 4-bit shift register The device is

useful in a wide variety of shifting counting and storage

applications It performs serial parallel serial-to-parallel or

parallel-to-serial data transfers

The 93L00 has two primary modes of operation shift right

(Q0

xQ1) and parallel load which are controlled by the

state of the Parallel Enable (PE) input When the PE input is

HIGH serial data enters the first flip-flop Q0 via the J and K

inputs

and

shifted

one

bit

the

direction

xQ1xQ2xQ3 following each LOW-to-HIGH

clock transition The JK inputs provide the flexibility of the

JK type input for special applications and the simple D-type

input for general applications by tying the two pins together

When the PE input is LOW the 93L00 appears as four com-

mon clocked D flip-flops The data on the parallel inputs

P0 – P3 is transferred to the respective Q0 – Q3 outputs fol-

lowing the LOW-to-HIGH clock transition Shift left opera-

tion (Q3

xQ2) can be achieved by tying the Qn outputs to

the Pnb1 inputs and holding the PE input LOW

All serial and parallel data transfers are synchronous occur-

ing after each LOW-to-HIGH clock transition Since the

93L00 utilizes edge triggering there is no restriction on the

activity of the J K Pn and PE inputs for logic operationex-

cept for the setup and release time requirements A LOW on

the asynchronous Master Reset (MR) input sets all Q out-

puts LOW independent of any other input condition

Truth Table

Operating

Inputs (MR e H)

Outputs

tna1

Mode

Shift Mode

Q0Q0Q1Q2Q2

XXXX

Q0Q0Q1Q2Q2

Parallel

Entry Mode

tna1 e Indicates state after next LOW-to-HIGH clock transition

H e HIGH Voltage Level

L e LOW Voltage Level

X e Immaterial

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