93L08 datasheet(3/4 Pages) NSC

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Switching Characteristics

VCC ea50V TA ea25 C (See Section 3 for waveforms and load configurations)

Symbol

Parameter

CL e 15 pF

Units

Min

Max

tPLH

Propagation Delay

tPHL

EntoQn

tPLH

Propagation Delay

tPHL

Dn to Qn

tPHL

Propagation Delay

MR to Qn

Functional Description

Data can be entered into the latch when both of the enable

inputs are LOW As long as this logic condition exists the

output of the latch will follow the input If either of the enable

inputs goes HIGH the data present in the latch at that time

is held in the latch and is no longer affected by data input

The master reset overrides all other input conditions and

forces the outputs of all the latches LOW when a LOW sig-

nal is applied to the Master Reset input

Truth Table

E0E1

Operation

Data Entry

Qnb1

Hold

Qnb1

Hold

Qnb1

Hold

Reset

Qnb1 e Previous Output State

Qn e Present Output State

H e HIGH Voltage Level

L e LOW Voltage Level

X e Immaterial

Logic Diagram

TLF9594 – 3

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