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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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ADIS16445/PCBZ Datenblatt(PDF) 5 Page - Analog Devices |
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ADIS16445/PCBZ Datenblatt(HTML) 5 Page - Analog Devices |
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5 / 22 page  Data Sheet ADIS16445 Rev. F | Page 5 of 22 TIMING SPECIFICATIONS TA = 25°C, VDD = +3.3 V, unless otherwise noted. Table 2. Parameter Description Normal Mode Burst Read Unit Min1 Typ Max Min1 Typ Max fSCLK Serial clock 0.01 2.0 0.01 1.0 MHz tSTALL Stall period between data 9 N/A2 µs tREADRATE Read rate 40 µs t CS Chip select to SCLK edge 48.8 48.8 ns tDAV DOUT valid after SCLK edge 100 100 ns tDSU DIN setup time before SCLK rising edge 24.4 24.4 ns tDHD DIN hold time after SCLK rising edge 48.8 48.8 ns tSCLKR, tSCLKF SCLK rise/fall times, not shown in timing diagrams 5 12.5 5 12.5 ns tDR, tDF DOUT rise/fall times, not shown in timing diagrams 5 12.5 5 12.5 ns tSFS CS high after SCLK edge 5 5 ns t1 Input sync positive pulse width 25 25 µs tSTDR Input sync to data ready valid transition 670 670 µs tNV Data invalid time 210 210 µs t3 Input sync period 910 910 µs 1 Guaranteed by design and characterization, but not tested in production. 2 When using the burst read mode, the stall period is not applicable. Timing Diagrams CS SCLK DOUT DIN 1 2 3 4 5 6 15 16 R/W A5 A6 A4 A3 A2 D2 MSB DB14 D1 LSB DB13 DB12 DB10 DB11 DB2 LSB DB1 tCS tSFS tDAV tDHD tDSU Figure 2. SPI Timing and Sequence CS SCLK tREADRATE tSTALL Figure 3. Stall Time and Data Rate CLOCK DATA READY t1 t3 tNV tSTDR Figure 4. Input Clock Timing Diagram |
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