PCB Layout Recommendations

Printed circuit board layout affects the performance of the

CLC005. The following guidelines will aid in achieving satis-

factory device performance.

•

Use a ground plane or power/ground plane sandwich de-

sign for optimum performance.

•

Bypass device power with a 0.01 µF monolithic ceramic

capacitor in parallel with a 6.8 µF tantalum electrolytic ca-

pacitor located no more than 0.1

″ (2.5 mm) from the de-

vice power pins.

•

Provide short, symmetrical ground return paths for:

— inputs,

— supply bypass capacitors and

— the output load.

•

Provide short, grounded guard traces located

— under the centerline of the package,

— 0.1

″ (2.5 mm) from the package pins

— on both top and bottom of the board with connecting

vias.

EVALUATION BOARD

A schematic, parts list and layout for a suitable evaluation

board are given on the following page. The artwork includes

trace, silk screen and ground layers. The individual printed

circuit board is available unassembled from National Semi-

conductor. To order this evaluation board, part number

CLC730056, contact your local sales representative or

the National Semiconductor Customer Response Center

in your area. (This evaluation board is identical to that for

the CLC007 for which some of the listed parts are not re-

quired.)

The evaluation board is a guide to proper circuit layout and

makes prototyping and measurement-taking easy. Since the

board is designed to accommodate many of the application

circuits possible with the CLC005, your particular application

may not require all of the listed parts or may require different

values. The evaluation board may be powered from standard

ECL supply voltages by installing the two jumpers in the lo-

cations labeled “−5”. For PECL supply voltages, install the

jumpers in the locations labeled “+5”.

DS100144-17

CLC005 Evaluation Board Schematic

9

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