VT82C586A datasheet(13/43 Pages) ETC

13 / 43 page

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VT82C586A

Preliminary Revision 0.1 October 13, 1996

-7-

Pinouts

Terminal Count. The VT82C586A asserts TC to DMA slaves as a terminal count

indicator.

IRQ15, 14, [11:

9], [7:3]

128-129, 127-

126, 61, 71-75

Interrupt Request. The IRQ signals provide both system board components and

ISA Bus I/O devices with a mechanism for asynchronously interrupting the CPU.

DRQ[7:5], [3:0]

132, 130, 57,

30, 7, 16, 59

DMA Request. The DREQ lines are used to request DMA services from the

VT82C586A’s DMA controller.

DACK[7:5],

[3:0]/

EXTSMI7-2,

DACEN

133, 131, 58,

31, 33, 18, 60

Multifunction Pins

Pin 135 (ROMCS#/KBCS#) strapped 1 at power up:

Normal Operation: Acknowledge. The DACK output lines indicate a request for

DMA service has been granted.

Power-up: Strap Inputs. Strapped inputs stored in configuration register 96h.

Pin 135 (ROMCS#/KBCS#) strapped 0 at power up:

Pin 60: DACEN. To enable external 137 for decoding DACKs from XD0-2.

Other pins: External SMI or General Purpose Inputs.

SPKR

134

Multifunction Pin

Normal Operation: Speaker Drive. The SPKR signal is the output of counter 2.

Power-up Strapping: 0/1 = Fixed/flexible IDE I/O base

Enhanced IDE Interface

DIORA#

Disk I/O Read A. Primary IDE channel drive read strobe.

DIOWA#

Disk I/O Write A. Primary IDE channel drive write strobe.

DIORB#

Disk I/O Read B. Secondary IDE channel drive read strobe.

DIOWB#

Disk I/O Write B. Secondary IDE channel drive write strobe.

DRDYA#

I/O Channel Ready A. IDE drive ready indicator.

DRDYB#

I/O Channel Ready B. IDE drive ready indicator from the second channel (required

for UltraDMA/33 IDE interface).

SOE#

System Address Transceiver Output Enable. This signal controls the output

enables of the 245 transceivers that interface the DD[15:0] signals to SA[15:0]. The

transceiver direction controls are driven by MASTER# with DD[15-0] connected to

the “A” side of the transceivers and SA[15-0] connected to the “B” side.

DDRQA

Disk DMA Request A. Primary IDE channel DMA request.

DDRQB

Disk DMA Request B. Secondary IDE channel DMA request.

DDACKA#

Disk DMA Acknowledge A. Primary IDE channel DMA acknowledge.

DDACKB#

Disk DMA Acknowledge B. Secondary IDE channel DMA acknowledge. This pin

is used as a power-up strap option: 0/1 = Fixed/relocatable IDE I/O address

Universal Serial Bus Interface

USBDATA0+

USB Port 0 Data +

USBDATA0-

USB Port 0 Data -

USBDATA1+

USB Port 1 Data +

USBDATA1-

USB Port 1 Data -

USBCLK

USB Clock. Clock input for Universal serial bus interface

Keyboard Interface

KBCK /

KA20G

108

Multifunction Pin. Function depends on enable/disable of internal KBC.

Internal KBC enabled: Keyboard Clock. Clock to keyboard interface.

Internal KBC disabled: Gate A20: Gate A20 output from external KBC

KBDT /

KBRC#

109

Multifunction Pin. Function depends on enable/disable of internal KBC.

Internal KBC enabled: Keyboard Data. Data to keyboard interface.

Internal KBC disabled: Keyboard Reset: Reset input from external KBC.

MSCK / IRQ1

110

Multifunction Pin. Function depends on enable/disable of internal KBC.

PS/2 mouse enabled: Mouse Clock. Clock to PS/2 mouse interface.

PS/2 mouse disable and internal KBC disabled: Interrupt Request 1.

IRQ 1 input from external KBC.

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