DIR1703

SLES007– JULY 2001

6

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basic operation theory

The DIR1703 is operated as either a PLL clock operation mode or a crystal clock operation mode. These basic

operation modes are user selectable.

Sampling period adaptive controlled tracking system (SpAct) is a newly developed clock recover architecture,

giving very low jitter clock from S/PDIF data input.

The DIR1703 has two PLLs, PLL1 and PLL2. SpAct is supplied with a 100 MHz executing clock from PLL1.

The DIR1703 requires system clock input for operation of SpAct at both the PLL clock operation mode and the

crystal clock operation mode. This system clock can be obtained by connecting a crystal resonator at the

XTI/XTO pins or applying an external clock input at the XTI pin as shown in Figure 1.

PLL2 generates the system clock SCKO by using the output signal of the SpAct. The source of SCKO, either

OSC (crystal) or PLL2, is selected by the CKSEL pin (called PLL clock operation mode and crystal clock

operation mode).

In the PLL clock operation mode, when the S/PDIF signal goes to noninput, SCKO may hold the latest tracked

frequency.

Also, the DIR1703 indicates the unlocked state by a high level output at the UNLOCK pin. When the S/PDIF

signal restarts, the analog PLL will lock to the incoming S/PDIF signal with very low jitter. The PLL lock-in time

is around 1 ms using the SpAct.

Then, the DIR1703 indicates the locked status by a low output at the UNLOCK pin. In this status, the BRATE

pins simultaneously indicate the bit rate of the incoming S/PDIF signal.

After RST (pin 21) is removed, SCKO is set to the default frequency, which can be selected by the BRSEL and

In the crystal clock operation mode, the crystal oscillator generates three audio clocks SCKO, BCKO, and

LRCKO. In this mode, DOUT is always set to mute (zero). BRATE and UNLOCK can be indicated according

to the incoming S/PDIF signal.

If CKSEL (pin 28) is connected to UNLOCK (pin 27), which indicates the S/PDIF decoding status and the PLL2

lock-state, the system clock source can be selected automatically when the S/PDIF signal is active and the bit

rate is detected.

Crystal

C 1

DIR1703

XTO

XTI

Open

DIR1703

XTO

XTI

C2

R1 = 1 MΩ,

C1, C2 = 10 TO 33 pF

XTAL

OSC

CIR

XTAL

OSC

CIR

External Clock

R1

Crystal Resonator Connection

External Clock Input

Figure 1. System Clock Connections