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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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MB9B360R Datenblatt(PDF) 32 Page - Cypress Semiconductor |
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MB9B360R Datenblatt(HTML) 32 Page - Cypress Semiconductor |
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32 / 166 page  Document Number: 002-04872 Rev.*A Page 32 of 166 MB9B360R Series Pin function Pin name Function description Pin No LQFP 120 LQFP 100 LQFP 80 QFP 100 BGA 112 BGA 144 External Bus MCSX0_0 External bus interface chip select output pin 95 80 65 58 A10 B10 MCSX1_0 96 81 66 59 A9 D9 MCSX2_0 101 86 - 64 C8 C8 MCSX3_0 100 85 - 63 B8 D8 MCSX4_0 98 83 - 61 C9 B9 MCSX5_0 97 82 67 60 B9 C9 MCSX6_0 104 89 70 67 C6 C7 MCSX7_0 106 91 72 69 B6 D6 MCSX8_0 35 30 - 8 L3 M3 MADATA00_0 External bus interface data bus (Address / data multiplex bus) 2 2 2 80 C1 C1 MADATA01_0 3 3 3 81 C2 C2 MADATA02_0 4 4 4 82 C3 D1 MADATA03_0 5 5 5 83 D1 D2 MADATA04_0 6 6 6 84 D2 D3 MADATA05_0 7 7 7 85 E1 E1 MADATA06_0 8 8 8 86 E2 E2 MADATA07_0 9 9 9 87 E3 E3 MADATA08_0 10 10 10 88 F1 E4 MADATA09_0 11 11 11 89 F2 F1 MADATA10_0 12 12 12 90 F3 F2 MADATA11_0 13 13 - 91 G1 F3 MADATA12_0 14 14 - 92 G2 F4 MADATA13_0 15 15 - 93 G3 G1 MADATA14_0 16 16 - 94 H2 G2 MADATA15_0 17 17 - 95 H3 G3 MDQM0_0 External bus interface byte mask signal output pin 93 78 63 56 B11 C10 MDQM1_0 92 77 62 55 A12 B13 MALE_0 External bus interface Address Latch enable output signal for multiplex 94 79 64 57 B10 A11 MRDY_0 External bus interface external RDY input signal 116 96 76 74 B3 B3 MCLKOUT_0 External bus interface external clock output pin 99 84 - 62 A8 A9 MNALE_0 External bus interface ALE signal to control NAND Flash output pin 18 - - - - G4 MNCLE_0 External bus interface CLE signal to control NAND Flash output pin 19 - - - - H1 MNREX_0 External bus interface read enable signal to control NAND Flash 21 - - - - H3 MNWEX_0 External bus interface write enable signal to control NAND Flash 20 - - - - H2 MOEX_0 External bus interface read enable signal for SRAM 114 94 74 72 B5 C4 MWEX_0 External bus interface write enable signal for SRAM 113 93 73 71 C5 B5 External Bus MSDCLK_0 SDRAM interface SDRAM clock output pin 23 18 - 96 J1 J1 MSDCKE_0 SDRAM interface SDRAM clock enable pin 24 19 - 97 J2 J2 MRASX_0 SDRAM interface SDRAM row address strobe pin 25 20 - 98 J3 J3 MCASX_0 SDRAM interface SDRAM column address strobe pin 26 21 - 99 K1 J4 MSDWEX_0 SDRAM interface SDRAM write enable pin 34 29 - 7 M3 N3 |
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