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Functional Description (Continued)

3.4.3.5

Power Management SMI Status Reporting

Registers

The CS5530 updates status registers to reflect the SMI

sources. Power management SMI sources are the device

idle timers, address traps, and general purpose I/O pins.

Power management events are reported to the processor

through the SMI# pin. It is active low. When an SMI is initi-

ated, the SMI# pin is asserted low and is held low until all

SMI sources are cleared. At that time, SMI# is deas-

serted.

All SMI sources report to the Top Level SMI Status Regis-

ter (F1BAR+Memory Offset 02h) and the Top Level SMI

Status Mirror Register (F1BAR+Memory Offset 00h). The

Top SMI Status and Status Mirror Registers are the top

level of hierarchy for the SMI Handler in determining the

source of an SMI. These two registers are identical except

that reading the register at F1BAR+Memory Offset 02h

clears the status.

Since all SMI sources report to the Top Level SMI Status

events requiring a second level of SMI status reporting.

The second level of SMI status reporting is set up very

much like the top level. There are two status reporting reg-

isters, one “read only” (mirror) and one “read to clear”.

The data returned by reading either offset is the same, the

difference between the two being that the SMI can not be

cleared by reading the mirror register.

Figure 3-7 shows an example SMI tree for checking and

clearing the source of General Purpose Timers and the

User Defined Trap generated SMI.

Table 3-32 shows the bit formats of the read to clear Top

Level SMI Status Register (F1BAR+Memory Offset 02h).

Table3-33showsthe bitformats of thereadto clear sec-

ond level SMI status registers. For information regarding

the location of the corresponding mirror register, refer to

the note in the footer of the register description.

Keep in mind, all SMI sources in the CS5530 are reported

into the Top Level SMI Status Registers (F1BAR+Memory

Offset 00h/02h); however, this discussion is regarding

power management SMIs. For details regarding audio

SMI events/reporting, refer to Section 3.7.2.2 “Audio SMI

Related Registers” on page 120.

Index 97h

GPIO Control Register 2 (R/W)

Reset Value = 00h

GPIO7 Edge Sense for SMI: Selects which edge transition of the GPIO7 pin generates an SMI:

0 = Rising; 1 = Falling.

Bit 3 must be set to enable this bit.

GPIO5 Edge Sense for SMI: Selects which edge transition of the GPIO5 pin generates an SMI:

0 = Rising; 1 = Falling.

Bit 2 must be set to enable this bit.

GPIO4 Edge Sense for SMI: Selects which edge transition of the GPIO4 pin generates an SMI:

0 = Rising; 1 = Falling.

Bit 1 must be set to enable this bit.

GPIO3 Edge Sense for SMI: Selects which edge transition of the GPIO3 pin will cause an external SMI:

0 = Rising; 1 = Falling.

Bit 0 must be set to enable this bit.

Enable GPIO7 as an External SMI Source: Allow GPIO7 to be an external SMI source and to generate an SMI on either

a rising or falling edge transition (depends upon setting of bit 7): 0 = Disable; 1 = Enable.

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status reporting is at F0 Index 84h/F4h[3].

Enable GPIO5 as an External SMI Source: Allow GPIO5 to be an external SMI source and to generate an SMI on either

a rising or falling edge transition (depends upon setting of bit 6): 0 = Disable; 1 = Enable.

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status reporting is at F0 Index 84h/F4h[2].

Enable GPIO4 as an External SMI Source: Allow GPIO4 to be an external SMI source and to generate an SMI on either

a rising- or falling-edge transition (depends upon setting of bit 5): 0 = Disable; 1 = Enable.

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status reporting is at F0 Index 84h/F4h[1].

Enable GPIO3 as an External SMI Source: Allow GPIO3 to be an external SMI source and to generate an SMI on either

a rising or falling edge transition (depends upon setting of bit 4) 0 = Disable; 1 = Enable.

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status reporting is at F0 Index 84h/F4h[0].

Note: For any of the above bits to function properly, the respective GPIO pin must be configured as an input (F0 Index 90h).

Table 3-31. GPIO Pin Configuration/Control Registers (Continued)

Bit

Description

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