ADS902

7

SBAS063A

THEORY OF OPERATION

The ADS902 is a high speed sampling ADC that utilizes a

pipeline architecture. The fully differential topology and

digital error correction guarantee 10-bit resolution. The

differential track/hold circuit is shown in Figure 1. The

switches are controlled by an internal clock which has a non-

overlapping two phase signal,

φ1 and φ2. At the sampling

time the input signal is sampled on the bottom plates of the

plates of the input capacitors are connected together and the

feedback capacitors are switched to the op amp output. At

pleting one acquisition cycle. The differential output is a

held DC representation of the analog input at the sample

time. The track/hold circuit also converts the single-ended

input signal into a fully differential signal for the subsequent

quantizer. Consequently, the input signal-to-noise perfor-

mance. Other parameters such as small-signal and full-

power bandwidth, and wideband noise are also defined in

this stage.

The pipelined quantizer architecture has 9 stages with each

stage containing a two-bit quantizer and a two bit digital-

to-analog converter, as shown in Figure 2. Each two-bit

FIGURE 2. Pipeline ADC Architecture.

FIGURE 1. Input Track/Hold Configuration with Timing

Signals.

φ1

φ1

φ2

φ1

φ1

φ1

φ1

φ1

φ2

φ1

φ2

φ1

φ2

IN

OUT

OUT

Bias

V

CM

V

CM

Bias

V

CM

C

H

C

I

C

I

C

H

Input Clock (50%)

Internal Non-overlapping Clock

Σ

+

–

B1 (MSB)

B2

B3

B4

B5

B6

B7

B8

B9

B10 (LSB)

2-Bit

DAC

2-Bit

Flash

Input

T/H

Digital Delay

x2

x2

2-Bit

DAC

2-Bit

Flash

Digital Delay

2-Bit

Flash

Digital Delay

2-Bit

DAC

2-Bit

Flash

Digital Delay

x2

IN

IN

STAGE 1

STAGE 2

STAGE 8

STAGE 9

Σ

+

–

Σ

+

–

(Opt.)