DP5380V datasheet(16/32 Pages) NSC

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70 Application Guide (Continued)

CSASI

4 IORQ*A7*A6*A5*A4*AEN ASI reg RW chip select

ADACK

4 IORQ*A7*A6*A5*A4*RD

mP pseudo-DMA cycle

IORQ*A7*A6*A5*A4*WR

0IORQ*A7*A6*A5*A4*RD mP pseudo-DMA with EOP

0IORQ*A7*A6*A5*A4*WR

0DDACK

DMAC DMA cycle

IF(AEN)AEOP

4 I0RQ*A7*A6*A5*A4*RD mP pseudo-DMA with EOP

0IORQ*A7*A6*A5*A4*WR a DEOP* AREADY

IF(DDACK*AREADY*INT)DEOP

4 DDACK*AREADY*INT

DMA cycle with error

CSDMA

4 I0RQ*A7*A6*A5*A4

DMAC register RW

DREADY

4 AREADY*INT

ASI not READY and not INT

0AREADY*DDACK

ASI not READY and DMA cycle active

IF(AEN)I0R

4 I0RQ*RD

mP IO Read cycle

IF(AEN)I0W

4 I0RQ*WR

mP IO Write cycle

IF(AEN)MEMR

4 I0RQ*RD

mP memory Read cycle

IF(AEN)MEMW

4 I0RQ*WR

mP memory Write cycle

FIGURE 73 PAL Equations

The mP and DMA signals are defined below

A7 – A4

Address bus

I0RQ

Memory IO cycle select

Read Strobe

Write Strobe

AEN

High DMA address enable asserted by DMAC

DDACK

DMAC DMA Acknowledge

CSDMA

DMA Chip Select

DREADY

Ready signal to DMACinserts wait-states when low

IOR IOW

IO data strobes tofrom DMAC

MEMR MEMW

Memory data strobe from DMAC

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