ADE3700XT datasheet(11/89 Pages) STMICROELECTRONICS

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ADE3700

Global Control

Functional Description

2.1

Global Control

The global control block is responsible for:

selecting clock sources

power control

I²C control

SCLK frequency synthesizer control

block by block synchronous reset generation

The global control block runs on the XCLK clock domain which is required to be active for

programming. The clock domains of all other blocks are set in the Global Control Block. For I²C

access, the requested block must be driven with a valid clock frequency greater than 10 MHz. Clock

domains are shown in Figure 2.

To program the SCLK frequency synthesizer to a desired frequency (fOUT, in MHz), the following

equations apply.

Figure 2: Global Control Block Diagram

Table 3: SCLK Frequency Synthesizer Programmable Values (Sheet 1 of 2)

Frequency Range

SDIV

fOUT < 8 x fXCLK AND fOUT ≥ 4 x fXCLK

fOUT < 4 x fXCLK AND fOUT ≥ 2 x fXCLK

ADE3700

I²C

PWM

Sync

Measure

Global

Sync

Re-Time

ADC (Analog)

ADC Digital I/F

Line Lock

PLL

Data

Measure

LCD Scaler

Flicker

Detection

Output

Sequencer

TCON

SCLK Freq.

Synthesizer

FM Freq.

Synthesizer

XCLK

Domain

INCLK

Domain

SCLK

Domain

DOTCLK

Domain

Data

MCU (SCL, SDA)

PC Analog

INR, G, B

V, H, Csync

ORA

OGA

OBA

ORB

OGB

OBB

OCLK

ODE

OHS

OVS

TCON

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