REV. A

ADP3421

–7–

THEORY OF OPERATION

Supply Voltages

The ADP3421 is optimized for use with, and specified at a

3.3 V supply, but can operate at up to 6 V at the expense of

increased quiescent current and minor tolerance degradation.

The ADP3410 MOSFET driver can accommodate up to 30 V

for driving the upper power MOSFET to 5 V above a 25 V rail.

Undervoltage Lockout

The undervoltage lockout (UVLO) circuit comprises the low

vides a system UVLO that monitors the battery voltage and

allows the converter operation to be disabled if the battery falls

below a preset threshold. A resistor divider to the UVLO pin

sets the UVLO-off level for the system comparing to a specified

triggers a specified current sink into the pin to be switched on.

This raises the UVLO-on threshold above the UVLO-off

threshold by the current sink values times the upper resistor of

the divider. So the resistor divider ratio at the UVLO pin is

used to set the UVLO threshold and the hysteresis.

Hysteresis for the system UVLO is recommended to prevent

oscillation due to nonzero battery impedance. If UVLO is trig-

gered during a condition where the battery is loaded by the

converter operation, the converter will turn off and the battery

voltage will then rise to a slightly higher level. A good design

will ensure that the hysteresis is sufficient to prevent the converter

from turning on again.

UVLO for VCC provides an internally specified UVLO thresh-

old for the ADP3421 to ensure that it only operates when the

applied VCC is sufficient to ensure that it can operate properly.

Activation of either UVLO circuit disables the reference and

bias circuits in the IC except for that which is needed for UVLO

detection.

Power Good

If the IC is enabled and is not in the UVLO mode and has fin-

ished its soft-start period, and if the core voltage is within

±10%

of the VID programmed value, then a high-level signal appears

at the PWRGD pin.

Power Good During VID Change

When a VID change occurs, the DAC output responds faster than

the output voltage, which is slew rate limited by the output

filter. In this case, PWRGD may momentarily go low. To avoid

system interruption, the PC power management system should

not respond to this glitch. The PWRGD signal corresponds to

V_GATE as specified in Intel’s Geyserville Voltage Regulator

specification. The glitch can be masked from the system by

using the appropriate system programming settings or by using

a functionally equivalent OR gate, which provides a blanking

signal for the specified latency period where the core voltage is

allowed to settle at its new value. Because of the minimal output

capacitor requirement, the response time of the core voltage is

well within the specified latency period and, when the power

converter is properly compensated, it does not exhibit any

overshoot.

VID-Programmed DAC Reference

This 5-bit digital-to-analog converter (DAC) serves as the

programmable reference source of the dc-dc converter. Pro-

gramming is accomplished by CMOS logic-level VID code

applied to the DAC input. The VID code corresponds to that

recommended in guidelines for the mobile Pentium

by Intel (see Table I).

Table I. VID Code

VID4

VID3

VID2

VID1

VID0

VOUT

0

0

0

0

0

2.000

0

0

0

0

1

1.950

0

0

0

1

0

1.900

0

0

0

1

1

1.850

0

0

1

0

0

1.800

0

0

1

0

1

1.750

0

0

1

1

0

1.700

0

0

1

1

1

1.650

0

1

0

0

0

1.600

0

1

0

0

1

1.550

0

1

0

1

0

1.500

0

1

0

1

1

1.450

0

1

1

0

0

1.400

0

1

1

0

1

1.350

0

1

1

1

0

1.300

0

111

1Off

*

1

0

0

0

0

1.275

1

0

0

0

1

1.250

1

0

0

1

0

1.225

1

0

0

1

1

1.200

1

0

1

0

0

1.175

1

0

1

0

1

1.150

1

0

1

1

0

1.125

1

0

1

1

1

1.100

1

1

0

0

0

1.075

1

1

0

0

1

1.050

1

1

0

1

0

1.025

1

101

11.00

1

1

1

0

0

0.975

1

1

1

0

1

0.950

1

1

1

1

0

0.925

1

111

1Off

*

*No CPU shutdown

Core Comparator

The core comparator is an ultrafast hysteretic comparator with

a typical propagation delay to the OUT pin of 15 ns at a 20 mV

overdrive.

This comparator is used with a switched hysteresis current for

controlling the main feedback loop, as described in the Main

Feedback Loop Operation section. This comparator has no

relation to the CORE pin, which is used only for core voltage

monitoring for the PWRGD function.

Current Limit Comparator

The current limit comparator monitors the voltage across the

and forces the OUT pin to low when the current exceeds the

peak current limit threshold. The current control is hysteretic,

with a valley current threshold equal to two-thirds of the peak

current limit threshold. When the sensed current signal falls to

two-thirds of the peak threshold, the OUT pin is allowed to go

high again, and the control of the main loop reverts back to the

core comparator.

Pentium is a registered trademark of Intel Corp.