ADS5500

SBAS303C − DECEMBER 2003 − REVISED MARCH 2004

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6

TIMING CHARACTERISTCS

16.5 Clock Cycles

Input Clock

Output Clock

Data Out

(D0−D13)

Analog

Input

Signal

Sample

N

N+ 1

N+ 2

N+ 3

N+4

N+ 15

N+ 1 6

N+1 7

N

− 17

N

− 16

N

− 15

N

− 13

N

− 3N − 2N − 1N

t

A

t

SETUP

t

HOLD

Data Invalid

t

PDI

NOTE: It is recommended that the loading at CLKOUT and all data lines are accurately matched to ensure that the above timing

matches closely with the specified values.

Figure 1. Timing Diagram

TIMING CHARACTERISTICS

Typ, min, and max values at TA = +25°C, full temperature range is TMIN = −40°C to tMAX = +85°C, sampling rate = 125MSPS, 50% clock duty

cycle, AVDD = DRVDD = 3.3V, DLL On, −1dBFS differential input, and 3VPP differential clock, unless otherwise noted.

PARAMETER

DESCRIPTION

MIN

TYP

MAX

UNIT

Switching Specification

Aperture delay, tA

Input CLK falling edge to data sampling point

1

ns

Aperture jitter (uncertainty)

Uncertainty in sampling instant

300

fs

Data setup time, tSETUP

Data valid to 50% of CLKOUT rising edge

2

ns

Data hold time, tHOLD

CLKOUT rising edge to data becoming invalid

1.7

ns

Data latency, tD(Pipe)

Input clock falling edge (on which sampling

takes place) to input clock rising edge (on

which the corresponding data is given out)

16.5

Clock Cycles

Propagation delay, tPDI

Input clock rising edge to data valid

7.5

ns

Data rise time

Data out 20% to 80%

2.5

ns

Data fall time

Data out 80% to 20%

2.5

ns

Output enable (OE) to

output stable delay

2

ms

SERIAL PROGRAMMING INTERFACE CHARACTERISTICS

The device has a three-wire serial interface. The device

latches the serial data SDATA on the falling edge of

serial clock SCLK when SEN is active.

SCLK shifts serial data at falling edge.

16 clocks.

while SEN is low.

bits, the excess bits are ignored.

a single active SEN pulse.