THS8200 datasheet(13/97 Pages) TI

Teilenummer	THS8200

Bauteilbeschribung	ALL FORMAT OVERSAMPLED COMPONENT VIDEO/PC GRAPHICS D/A SYSTEM WITH THREE 11-BIT DACS,CGMS DATA INSERTION

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Hersteller	TI [Texas Instruments]

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13 / 97 page

3–1

3 THS8200 Functional Overview

ifir

dly

eav

sav

scl_en

scl_out

scl_in

sda_en

sda_out

sda_in

rcr_in

bcb_in

gy_in

vs_in

hs_in

databus_in

databus_out

address

addr_en

ready

dg_bias

dr_bias

db_bias

digbypass

Three Channel DACs

4:2:2 to 4:4:4

I2C

Slave

arst_func_n

ifir12_bypass

ifir35_bypass

Color

Space

Convertor

ifir

Clip

Scale

Multiplier

Display

Timing

Generator

digbypass

csmouts

ifirouts

dmanouts

dtg_data

dg_bias

vs_out

hs_out

dlclko

do[9:0]

db_bias

dr_bias

clk_fx2

clk_f

cdrv

clk_h

clkin

tstmode

cgen

clkin

Clock Generator

Offset Binary Signals

cscouts

Figure 3–1. Functional Block Diagram

3.1

Data Manager (DMAN)

The data manager is the block that transforms the selected input video data format present on the chip input bus(es)

to an internal 10-bit three-channel representation. Supported input formats include 10/8 bit ITU-R.BT656 with

embedded sync codes, 15-/16- or 24-/30-bit RGB with external sync, 20-/16-bit SMPTE274M/296M with embedded

sync codes, as well as 20-/16-bit YCbCr 4:2:2 with external sync. The user can optionally include a 4:2:2 to 4:4:4

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