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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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VT82C596B Datenblatt(PDF) 40 Page - List of Unclassifed Manufacturers |
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VT82C596B Datenblatt(HTML) 40 Page - List of Unclassifed Manufacturers |
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40 / 96 page  VT82C596B Revision 0.3 June 17, 1999 -34- Register Descriptions - Legacy I/O Ports 7HFKQRORJLHV ,QF :H &RQQHFW :H &RQQHFW CMOS / RTC Registers Port 70 - CMOS Address ................................................. WO 7NMI Disable......................................................... WO 0 Enable NMI Generation. NMI is asserted on encountering IOCHCK# on the ISA bus or SERR# on the PCI bus. 1 Disable NMI Generation ........................default 6-0 CMOS Address (lower 128 bytes)....................... WO Port 71 - CMOS Data........................................................RW 7-0 CMOS Data (128 bytes) Note: Ports 70-71 may be accessed if Rx5A bit-2 is set to one to select the internal RTC. If Rx5A bit-2 is set to zero, accesses to ports 70-71 will be directed to an external RTC. Port 72 - CMOS Address ..................................................RW 7-0 CMOS Address (256 bytes)................................. RW Port 73 - CMOS Data........................................................RW 7-0 CMOS Data (256 bytes) Note: Ports 72-73 may be accessed if Rx5A bit-2 is set to one to select the internal RTC. If Rx5A bit-2 is set to zero, accesses to ports 72-73 will be directed to an external RTC. Port 74 - CMOS Address ..................................................RW 7-0 CMOS Address (256 bytes)................................. RW Port 75 - CMOS Data........................................................RW 7-0 CMOS Data (256 bytes) Note: Ports 74-75 may be accessed only if Function 0 Rx5B bit-1 is set to one to enable the internal RTC SRAM and if Rx48 bit-3 (Port 74/75 Access Enable) is set to one to enable port 74/75 access. Note: Ports 70-71 are compatible with PC industry- standards and may be used to access the lower 128 bytes of the 256-byte on-chip CMOS RAM. Ports 72-73 may be used to access the full extended 256- byte space. Ports 74-75 may be used to access the full on-chip extended 256-byte space in cases where the on-chip RTC is disabled. Note: The system Real Time Clock (RTC) is part of the “CMOS” block. The RTC control registers are located at specific offsets in the CMOS data area (0- 0Dh and 7D-7Fh). Detailed descriptions of CMOS / RTC operation and programming can be obtained from the VIA VT82887 Data Book or numerous other industry publications. For reference, the definition of the RTC register locations and bits are summarized in the following table: Offset Description Binary Range BCD Range 00 Seconds 00-3Bh 00-59h 01 Seconds Alarm 00-3Bh 00-59h 02 Minutes 00-3Bh 00-59h 03 Minutes Alarm 00-3Bh 00-59h 04 Hours am 12hr: 01-1Ch 01-12h pm 12hr: 81-8Ch 81-92h 24hr: 00-17h 00-23h 05 Hours Alarm am 12hr: 01-1Ch 01-12h pm 12hr: 81-8Ch 81-92h 24hr: 00-17h 00-23h 06 Day of the Week Sun=1: 01-07h 01-07h 07 Day of the Month 01-1Fh 01-31h 08 Month 01-0Ch 01-12h 09 Year 00-63h 00-99h 0A Register A 7UIP Update In Progress 6-4 DV2-0 Divide (010=ena osc & keep time) 3-0 RS3-0 Rate Select for Periodic Interrupt 0B Register B 7SET Inhibit Update Transfers 6PIE Periodic Interrupt Enable 5AIE Alarm Interrupt Enable 4UIE Update Ended Interrupt Enable 3SQWE No function (read/write bit) 2DM Data Mode (0=BCD, 1=binary) 1 24/12 Hours Byte Format (0=12, 1=24) 0DSE Daylight Savings Enable 0C Register C 7IRQF Interrupt Request Flag 6PF Periodic Interrupt Flag 5AF Alarm Interrupt Flag 4UF Update Ended Flag 3-0 0 Unused (always read 0) 0D Register D 7 VRT Reads 1 if VBAT voltage is OK 6-0 0 Unused (always read 0) 0E-7C Software-Defined Storage Registers (111 Bytes) Offset Extended Functions Binary Range BCD Range 7D Date Alarm 01-1Fh 01-31h 7E Month Alarm 01-0Ch 01-12h 7F Century Field 13-14h 19-20h 80-FF Software-Defined Storage Registers (128 Bytes) (See also Function 0 Rx5B[3] and Rx77[2-1]) Table 5. CMOS Register Summary |
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