TMS320DM641 datasheet(21/171 Pages) TI

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Functional Block Diagram

June 2003 − Revised August 2004

SPRS222C

HPI†

Test

C64x DSP Core

Data Path B

B Register File

B31−B16

B15−B0

Instruction Fetch

Instruction Dispatch

Advanced Instruction Packet

Instruction Decode

Data Path A

A Register File

A31−A16

A15−A0

Power-Down

Logic

.L1

.S1

.M1 .D1

.D2

.M2

.S2

.L2

SDRAM

FIFO

SBSRAM

SRAM

L1P Cache

Direct-Mapped

16K Bytes Total

Control

Registers

Control

Logic

L1D Cache 2-Way Set-Associative

16K Bytes Total

Advanced

In-Circuit

Emulation

Interrupt

Control

TMS320DM641/TMS320DM640

Enhanced

DMA

Controller

(EDMA)

Cache

Memory

128KBytes

PLL

(x1, x6, x12)

Timer 2

EMIF A

ZBT SRAM

Timer 1

Boot Configuration

ROM/FLASH

I/O Devices

McBSP1‡

McASP0

Data

AND

EMAC

MDIO

GP0

I2C0

See Note A

McBSP0‡

McASP0

Control

AND

Timer 0

8-Bit

VP0

8-Bit

VP1†

VCXO

Interpolated

Control Port

(VIC)

† HPI and VP1 are not supported on the DM640 device.

‡ McBSPs: Framing Chips − H.100, MVIP, SCSA, T1, E1; AC97 Devices; SPI Devices; Codecs

NOTE A: The Video Port 0 (VP0) peripheral is muxed with the McBSP0 peripheral and the McASP0 control pins (DM641/DM640). The Video

Port 1 (VP1) peripheral is muxed with the McBSP1 peripheral and the McASP0 data pins (DM641 only). For more details on the

multiplexed pins of these peripherals, see the Device Configurations section of this data sheet.

Figure 1−1. Functional Block Diagram

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