TAS3208IPZP datasheet(45/79 Pages) TI1

45 / 79 page

TAS3208

www.ti.com

SLES201E

– JANUARY 2007 – REVISED MARCH 2011

ELECTRICAL CHARACTERISTICS

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

3.3-V TTL

IOH = –4 mA

2.4

VOH

High-level output voltage

1.8-V LVCMOS (XTL_OUT)

IOH = –0.55 mA

1.44

3.3-V TTL

IOL = 4 mA

0.5

VOL

Low-level output voltage

1.8-V LVCMOS (XTL_OUT)

IOL = 0.75 mA

0.396

IOZ

High-impedance output current 3.3-V TTL

±20

µA

1.8-V LVCMOS (XTL_IN)

±1

IIL

Low-level input current(1)

VI = VIL

µA

3.3-V TTL

±1

1.8-V LVCMOS (XTL_IN)

±1

IIH

High-level input current(2)

VI = VIH

µA

3.3-V TTL

±1

DSP clock = 135 MHz,

IDVDD

Digital supply current

LRCLKIN/LRCLKOUT = 48 KHz,

200

XTALI = 24.288 MHz

DSP clock = 135 MHz,

IAVDD

Analog supply current

LRCLKIN/LRCLKOUT = 48 KHz,

XTALI = 24.288 MHz

IDVDD

Digital supply current

RESET = LOW

0.1

IAVDD

Analog supply current

RESET = LOW

(1)

Value given is for those input pins that connect to an internal pullup resistor, as well as an input buffer. For inputs that have a pulldown

resistor or no resistor, IIL = ±1 µA.

(2)

Value given is for those input pins that connect to an internal pulldown resistor, as well as an input buffer. For inputs that have a pullup

resistor or no resistor, IIH = ± 1 µA.

TIMING REQUIREMENTS

– MASTER CLOCK SIGNALS

over recommended operating conditions (see Figure 33)

MIN

TYP

MAX

UNIT

24.576

fXTALI

XTALI frequency (1/ tcyc1)

(1)

MHz

(512 Fs)

tcyc1

XTALI cycle time(2)

1/(512 Fs)

fMCLKIN

MCLKIN frequency (1/ tcyc2)

256 Fs

MHz

twMCLKIN

MCLKIN pulse duration(3)

0.4

× tcyc2

0.6

× tcyc2

fMCLKOUT

MCLKOUT frequency(1/ tcyc3)

256 Fs

MHz

trMCLKOUT

MCLKOUT rise time

CL = 30 pF

tfMCLKOUT

MCLKOUT fall time

CL = 30 pF

twMCLKOUT

MCLKOUT pulse duration(4)

0.4

× tcyc3

0.6

× tcyc3

MCLKOUT jitter

XTALI master clock source

Delay time, MCLKIN rising edge to

tdMI–MO

MCLKOUT = MCLKIN

MCLKOUT rising edge (5)

(1)

Frequency tolerance is

±100 ppm (or better) at 25°C.

(2)

tcyc1 = 1/ fXTALI

(3)

tcyc2 = 1/ fMCLKIN

(4)

tcyc3 = 1/ fMCLKOUT

(5)

When MCLKOUT is derived from MCLKIN, MCLKOUT jitter = MCLKIN jitter. MCLKOUT has the same duty cycle as MCLKIN when

MCLKOUT = MCLKIN.

TIMING REQUIREMENTS

– RESET

with respect to DVDD power good (see Figure 34)

MIN

MAX

UNIT

tpgw(L)

Minimum pulse duration, RESET low following DVDD = 3.3 V

100

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