| Datenblatt-Suchmaschine für elektronische Bauteile |
|
LP3913 Datenblatt(PDF) 49 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
LP3913 Datenblatt(HTML) 49 Page - Texas Instruments |
|
49 / 70 page ![]() LP3913 www.ti.com SNVS489I – NOVEMBER 2006 – REVISED SEPTEMBER 2013 LDO1 Control Register LDO1 can be configured through its own I2C control register. The output voltage is programmable in steps of 100 mV from 1.2V to 3.3V. LDO1 gets enabled during the power-on sequence. Disable/enable control is provided through bit D5 in the LDO1 control register after selecting the appropriate D4–0 settings, which determine the output voltage. The output voltage can be altered while LDO1 is enabled. When LDO1 is disabled it shunts the output to AGND with a RSHUNT = 200Ω (Max.). LDO1 Control Register (08)h D7–6 D5 D4–0 Access Read Only 0 R/W Data Reserved Operation LDO1 Output Voltage (V) 0: disable 5’h00 1.2 1: enable 5’h01 1.3 5’h02 1.4 5’h03 1.5 5’h04 1.6 5’h05 1.7 5’h06 1.8 5’h07 1.9 5’h08 2.0 5’h09 2.1 5’h0A 2.2 5’h0B 2.3 5’h0C 2.4 5’h0D 2.5 5’h0E 2.6 5’h0F 2.7 5’h10 2.8 5’h11 2.9 5’h12 3.0 5’h13 3.1 5’h14 3.2 5’h15 –5’h1F 3.3 Reset n/a 1 5’h08 LDO2 Control Register LDO2 can be configured through its own I2C control register. The output voltage is programmable in steps of 100mV from 1.3V to 3.3V. LDO2 is by default disabled and can be enabled by setting bit D5 in the control register after selecting the appropriate D4–0 settings, which determine the output voltage. LDO2 can also be enabled through the external LDO2EN pin, which is the default enable control. With a logic 0 programmed to bit D5 in the corresponding control register, enable/disable control is passed onto the LDO2EN pin; a logic 1 applied to this pin enables LDO2 while a logic 0 disables the LDO2. Setting D5 to 1 in the LDO2 control register enables LDO2, regardless of the state of the LDO2EN pin. If the system designer permanently connects the LDO2EN pin to GND, then D5 is simply a enable/disable control bit. If the system design permanently connects the enable pin to VDD, then the LDO is enabled during the power-on sequence and will always be on, regardless of the state of bit D5 in the LDO2 control register. In that particular case, the LDO2 is sequenced with the same timing as LDO1 (see Power On/Off Sequencing). The output voltage can be altered while LDO2 is enabled. When LDO2 is disabled it shunts the output to AGND with a RSHUNT = 200Ω (Max.). Copyright © 2006–2013, Texas Instruments Incorporated Submit Documentation Feedback 49 Product Folder Links: LP3913 |
|
Link URL |
| War ALLDATASHEET hilfreich? [ DONATE ] |
Über Alldatasheet | Werbung | Kontakt | Privatsphäre und Datenschutz | Link zum Datenblatt | Linktausch | Hersteller All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |