CLC5902 datasheet(12/28 Pages) NSC

12 / 28 page

Rev. 3.05 May 27, 1999

Detailed Description

Control Interface

The CLC5902 is configured by writing control informa-

tion into 148 control registers within the chip. The con-

tents of these control registers and how to use them are

described in Table 5. The registers are written to or read

from using the D[7:0], A[7:0], CE, RD and WR pins (see

Table 1 for pin descriptions). This interface is designed to

allow the CLC5902 to appear to an external processor as a

memory mapped peripheral. See Figure 14 for details.

The control interface is asynchronous with respect to the

system clock, CK. This allows the registers to be written

or read at any time. In some cases this might cause an

invalid operation since the interface is not internally syn-

chronized. In order to assure correct operation, SI must be

asserted after the control registers are written.

The D[7:0], A[7:0], WR, RD and CE pins should not be

driven above the positive supply voltage.

Master Reset

A master reset pin, MR, is provided to initialize the

CLC5902 to a known condition and should be strobed

after power up. This signal will clear all sample data and

all user programmed data (filter coefficients and AGC set-

tings). All outputs will be disabled (tri-stated). ASTROBE

and BSTROBE will be asserted to initialize the DVGA

values. Table 5 describes the control register default val-

ues.

Synchronizing Multiple CLC5902 Chips

A system containing two or more CLC5902 chips will

need to be synchronized if coherent operation is desired.

To synchronize multiple CLC5902 chips, connect all of

the sync input pins together so they can be driven by a

common sync strobe. Synchronization occurs on the rising

edge of CK when SI goes back high. When SI is asserted

all sample data will be flushed immediately, the numeri-

cally controlled oscillator (NCO) phase offset will be ini-

tialized, the NCO dither generators will be reset, and the

CIC decimation ratio will be initialized. Only the configu-

ration data loaded into the microprocessor interface

remains unaffected.

SI may be held low as long as desired after a minimum of

4 CK periods.

Input Source

The input crossbar switch allows either AIN, BIN, or a

test register to be routed to the channel A or channel B

AGC/DDC. The AGC outputs, AGAIN and BGAIN, are

not switched. If AIN and BIN are exchanged the AGC

loop will be open and the AGCs will not function properly.

AIN and BIN should meet the timing requirements shown

in Figure 7.

Selecting the test register as the input source allows the

AGC or DDC operation to be verified with a known input.

See the test and diagnostics section for further discussion.

Down Converters

A detailed block diagram of each DDC channel is shown

in Figure 15. Each down converter uses a complex NCO

and mixer to quadrature downconvert a signal to base-

band. The “FLOAT TO FIXED CONVERTER” treats the

15-bit mixer output as a mantissa and the AGC output,

EXP, as a 3-bit exponent. It performs a bit shift on the data

based on the value of EXP. This bit shifting is used to

expand the compressed dynamic range resulting from the

DVGA operation. The DVGA gain is adjusted in 6dB

steps which are equivalent to each digital bit shift.

The exponent (EXP) can be forced to its maximum value

by setting the EXP_INH bit. If

is the DDC input,

the signal after the “FLOAT TO FIXED CONVERTER” is

EQ. 1

for the I component. Changing the ‘cos’ to ‘sin’ in this

equation will provide the Q component.

NCO

FREQ_A

PHASE_A

Data @ FCK

EXPONENT

EXP

OUTPUT

CIRCUIT

Figure 15

CLC5902 Down Converter, Channel A (Channel B is identical)

SIN

COS

(from AGC)

3 n

()

in n

()

MUXA

= FS (FSAMPLE)

Data @ FCK/N

Data @ FCK/N*2

Data @ FCK/N*2*F2_DEC

= OFS (Output FSAMPLE)

N = DEC + 1

in n

()

3 n

() x

in n

()

ωn

()

cos

•

EXP

•

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