LP3952 datasheet(34/46 Pages) TI1

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LP3952

SNVS518A – JULY 2007 – REVISED MARCH 2013

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R1/G1/B1 BLINK (01H, 03H, 05H) – BLINKING ON/OFF TIME CONTROL REGISTER

R1/G1/B1_ON[3:0]

R1/G1/B1_OFF[3:0]

rw-0

RGB1 ON and OFF time

Bits

ON/OFF time

0000

0001

0010

2.5%

0011

0100

7.5%

0101

10%

R1_ON[3:0], R1_OFF[3:0]

0110

15%

G1_ON[3:0], G1_OFF[3:0]

Bits 7-4, 3-0

0111

20%

B1_ON[3:0], B1_OFF[3:0]

1000

30%

1001

40%

1010

50%

1011

60%

1100

70%

1101

80%

1110

90%

1111

100%

R1/G1/B1 CYCLE (02H, 04H, 06H) – BLINKING CYCLE CONTROL REGISTER

R1/G1/B1_CYCL

R1/G1/B1_CYCLE[2:0]

E_EN

r-0

rw-0

R1_CYCLE_EN

Bit 3

Blinking enable

G1_CYCLE_EN

0 = disabled, output state is defined with RGB registers

B1_CYCLE_EN

1 = enabled, output state is defined with blinking cycle

R1_CYCLE[2:0]

Bits 2-0

RGB1 cycle time

G1_CYCLE[2:0]

Bits

Blinking cycle time

Blinking frequency

B1_CYCLE[2:0]

000

0.1s

10 Hz

001

0.25s

4 Hz

010

0.5s

2 Hz

011

1 Hz

100

0.5 Hz

101

0.33 Hz

110

0.25 Hz

111

0.2 Hz

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