SP5730ASLASHKGSLASHMP2S datasheet(5/12 Pages) ZARLINK

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SP5730

Datasheet

Address

Programmable divider

Control data

Byte 1

Byte 2

Byte 3

Byte 4

Byte 5

214

213

212

211

MA1

210

MA0

Table 3 - Write data format (MSB transmitted first)

MSB

LSB

Key to Table 3.

Acknowledge bit

MA1, MA0

Variable address bits (see Table 5)

214-20

Programmable division ratio control bits

R4-R0

Reference division ratio select (see Table 2)

C1, C0

Charge pump current select (see Table 7)

Reference oscillator output enable

REF/COMP output select when RE=1 (see Table 8)

T1-T0

Test mode control bits (see Table 6)

P3-P0

P3, P2, P1 and P0 port output states

Address

Status byte

POR

Byte 1

Byte 2

MA1

MA0

MSB

LSB

Table 4 - Read data format (MSB transmitted first)

Key to table 4,

Acknowledge bit

MA1, MA0

Variable address bits (see Table 5)

POR

Power On Reset indicator

Phase lock flag

Table 5 - Address selection

* Programmed by connecting a 15k

Ω resistor from pin 10 to V

MA1

0 to 0·1VCC

Open circuit

0·4VCC to 0·6VCC *

0·9VCC to VCC

Address input voltage level

MA0

Current (

µA)

Min.

Typ.

Max.

±116

±247

±517

±1087

±155

±330

±690

±1450

±194

±412

±862

±1812

Table 7 - Charge pump current

* Clocks need to be present on crystal and RF inputs to enable

charge pump test modes and to toggle Status byte bit FL.

X = don’t care

Table 6 - Test modes

RE•RS

Test mode description

Normal operation

Normal operation, P0 = fPD/2

Charge pump sink*, FL = ‘0’

Charge pump source*, FL = ‘0’

Charge pump disabled*, FL = ‘1’

Table 8 - REF/COMP output

REF/COMP output

High impedance

fREF selected

fCOMP selected

X = don’t care

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