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DEM-PCM3500 Datenblatt(PDF) 2 Page - Texas Instruments |
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DEM-PCM3500 Datenblatt(HTML) 2 Page - Texas Instruments |
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2 / 4 page ![]() 2 ® DEM-PCM3500 FIGURE 1. Schematic. CONNECTORS CN1 is the power supply connector for the DEM-PCM3500. The +VCC pin may be set between +2.7V and +3.6V. The GND pin should be connected to the negative (–) or ground terminal of the power supply or battery, and functions as the analog ground connection. CN2 is the host interface connector. It includes connections for the serial interface and system clock input /output. The connec- tor pins correspond directly to the pin names of the PCM3500. Refer to the PCM3500 data sheet for more details regarding the operation and requirements for these connections. CN3 is the analog input connector. The VIN pin is connected to the PCM3500 analog-to-digital converter input, while the GND pin is connected to analog ground. The full-scale input voltage for VIN is 0.6VCC (in Vp-p), or 1.8Vp-p for a +3V power supply. CN4 is the analog output connector. The VOUT pin is con- nected to the PCM3500 digital-to-analog converter output, while the GND pin is connected to analog ground. The full- scale output voltage at VOUT is typically 0.6VCC (in Vp-p), or 1.8Vp-p for a +3V power supply. DIP SWITCH SETTINGS Table I shows the function of each switch setting for SW1. Each switch corresponds directly to a pin of the PCM3500. Refer to the PCM3500 data sheet for more details regarding the operation and requirements for these pin functions. TABLE I. DIP Switch Settings. SW1 DESCRIPTION PWDN H = Power Down Disabled (normal operation) L = Power Down Enabled LOOP H = ADC-to-DAC Loop Back Enabled L = ADC-to-DAC Loop Back Disabled HPFD H = ADC High Pass Filter Disabled L = ADC High Pass Filter Enabled T/S H = Time Slot Mode Enabled L = Time Slot Mode Disabled M/S H = Master Mode Enabled L = Slave Mode Enabled CRYSTAL OSCILLATOR OPERATION The PCM3500 contains an internal crystal oscillator circuit. The oscillator can be used to generate the 512fS system clock (512 times the desired sample frequency). The crystal value must be equal to 512fS. A fundamental mode, parallel resonant crystal is recommended. The load capacitors, CS, should be set in the range from 10pF – 33pF, with 22pF being the typical value. When using the crystal oscillator, BCK and FS should be derived from SCKIO when using Slave mode. Alternatively, the PCM3500 may be set to Master mode so that the BCK and FS are generated by the CODEC itself. V COM V REF1 V REF2 V IN AGND M/S TSC BCK FS DIN DOUT FSO V CC AGND V OUT AGND PDWN LOOP HPFD XTI XTO SCKIO DGND V DD 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 U1 PCM3500 PWDN SW1 DSS105 LOOP HPFD DOUT FSO FS DIN BCK SCKO GND XTI CN2 VH8 V OUT GND CN4 VH2 C 1 1 µF C 2 2.2 µF + C 3 4.7 µF + C 4 4.7 µF + + SCKIO XTI C 6 0.1 µF C 7 4.7 µF + C 11 1 µF + V IN GND CN3 VH2 GND V CC CN1 VH2 PDWN LOOP HPFD SCKIO + C 8 4.7 µF C 5 0.1 µF + C 10 0.1 µF C 9 100 µF C S C S XTAL OPTIONAL XTI |
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