PCM3500 datasheet(21/26 Pages) TI

21 / 26 page

PCM3500

VREF1 (pin 2) and VREF2 (pin 3) are reference voltages used

by the delta-sigma modulators. They are brought out strictly

for decoupling purposes. VREF1 and VREF2 are not to be

used to bias external circuits. A 1

µF to 10µF aluminum

electrolytic or tantalum capacitor is recommended for

decoupling on each pin. These capacitors should be located

as close as possible to pins 2 and 3.

Power Supplies and Grounding

VCC (pin 24) and VDD (pin 13) should be connected directly

to the +2.7V to +3.6V analog power supply, as shown in

Figure 16. The AGNDs (pins 5, 21, and 23) and DGND (pin

14) should be connected directly to the analog ground.

Power supply bypass capacitors should be located as close

to the power supply pins as possible in order to ensure a low

impedance connection. A combination of a 10

µF aluminum

electrolytic or tantalum capacitor in parallel with a 0.1

µF

ceramic capacitor is recommended for both VCC and VDD.

VDD and VCC should not be connected to separate digital and

analog power supplies. This can lead to an SCR latch-up

condition, which can cause either degraded device perfor-

mance or catastrophic failures.

PCB LAYOUT GUIDELINES

The recommended PCB layout technique is shown in Figure

18. The analog and digital section of the board are separated

by a split ground plane, with the PCM3500 positioned

entirely over the analog section of the board. The AGNDs

(pins 5, 20, and 23) and DGND (pin 14) are connected

directly to the analog ground plane. The power supply pins,

VCC (pin 13) and VDD (pin 24), are routed directly to the

+2.7V to +3.6V analog power supply using wide copper

traces (100 mils or wider recommended) or a power plane.

Power supply bypass and reference decoupling capacitors

are shown located as close as possible to the PCM3500.

The PCM3500 is oriented so that the digital pins are facing

the ground plane split. Digital connections should be made

as short and direct as possible to limit high frequency

radiation and coupling. Series resistors (from 20

Ω to 100Ω)

may be put in series with the system clock, FS, BCK, and

FSO lines to reduce or eliminate overshoot on clock edges,

further reducing radiated emissions. The split ground plane

should be connected at one point by a trace, wire, or ferrite

bead. Often the board will be designed to have several

jumper points for the common ground connection, so that

the best performance can be derived through experimenta-

tion.

An alternative technique, using a single power supply or

battery, is shown in Figure 19. This technique is more

suitable for portable applications.

FIGURE 18. Recommended PCB Layout Technique.

FIGURE 19. PCB Layout Using a Single-Supply or Battery.

PCM3500

AGND

Analog

Ground

Digital

Ground

DGND

Digital Power

Supply

Analog Power

Supply

+3.3V

Common

Connection

DIGITAL SECTION

ANALOG SECTION

Host

and

Logic

+3.3V

Digital I/Os

Split Grounds

PCM3500

AGND

Split Grounds

Ferrite

Beads

Analog

Ground

Digital

Ground

DGND

DIGITAL SECTION

ANALOG SECTION

Host

and

Logic

Common

Supply

Digital I/Os

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