PCM1793

SLES076A − MARCH 2003 − REVISED JANUARY 2004

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13

SYSTEM CLOCK AND RESET FUNCTIONS

System Clock Input

The PCM1793 requires a system clock for operating the digital interpolation filters and advanced segment DAC

modulators. The system clock is applied at the SCK input (pin 5). The PCM1793 has a system clock detection circuit

that automatically senses which frequency the system clock is operating. Table 1 shows examples of system clock

frequencies for common audio sampling rates.

Figure 22 shows the timing requirements for the system clock input. For optimal performance, it is important to use

a clock source with low phase jitter and noise. One of the Texas Instruments’ PLL1700 family of multiclock generators

is an excellent choice for providing the PCM1793 system clock.

Table 1. System Clock Rates for Common Audio Sampling Frequencies

SAMPLING FREQUENCY

SYSTEM CLOCK FREQUENCY (FSCK) (MHZ)

SAMPLING FREQUENCY

128 fS

192 fS

256 fS

384 fS

512 fS

768 fS

32 kHz

4.096

6.144

8.192

12.288

16.384

24.576

44.1 kHz

5.6488

8.4672

11.2896

16.9344

22.5792

33.8688

48 kHz

6.144

9.216

12.288

18.432

24.576

36.864

96 kHz

12.288

18.432

24.576

36.864

49.152

73.728

192 kHz

24.576

36.864

49.152

73.728

(1)

(1)

(1) This system clock rate is not supported for the given sampling frequency.

t(SCKH)

System Clock (SCK)

t(SCKL)

2.0 V

0.8 V

H

L

t(SCY)

PARAMETERS

MIN

MAX

UNITS

t(SCY)

System clock pulse cycle time

13

ns

t(SCKH) System clock pulse duration, HIGH

5

ns

t(SCKL) System clock pulse duration, LOW

5

ns

Figure 22. System Clock Input Timing

Power-On and External Reset Functions

the power-on reset function is enabled. The initialization sequence requires 1024 system clocks from the time

The PCM1793 also includes an external reset capability using the RST input (pin 6). This allows an external controller

or master reset circuit to force the PCM1793 to initialize to its default reset state.

Figure 24 shows the external reset operation and timing. The RST pin is set to logic 0 for a minimum of 20 ns. The

RST pin is then set to a logic 1 state, thus starting the initialization sequence, which requires 1024 system clock

periods. The external reset is especially useful in applications where there is a delay between the PCM1793 power

up and system clock activation.