ST72561 datasheet(68/262 Pages) STMICROELECTRONICS

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ST72561

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PWM AUTO-RELOAD TIMER (Cont’d)

Input Capture Function

Input Capture mode allows the measurement of

external signal pulse widths through ARTICRx

registers.

Each input capture can generate an interrupt inde-

pendently on a selected input signal transition.

This event is flagged by a set of the corresponding

CFx bits of the Input Capture Control/Status regis-

ter (ARTICCSR).

These

input

capture

interrupts

are

enabled

through the CIEx bits of the ARTICCSR register.

The active transition (falling or rising edge) is soft-

ware programmable through the CSx bits of the

ARTICCSR register.

The read only input capture registers (ARTICRx)

are used to latch the auto-reload counter value

when a transition is detected on the ARTICx pin

(CFx bit set in ARTICCSR register). After fetching

the interrupt vector, the CFx flags can be read to

identify the interrupt source.

Note: After a capture detection, data transfer in

the ARTICRx register is inhibited until the next

read (clearing the CFx bit).

The timer interrupt remains pending while the CFx

flag is set when the interrupt is enabled (CIEx bit

set). This means, the ARTICRx register has to be

read at each capture event to clear the CFx flag.

The timing resolution is given by auto-reload coun-

ter cycle time (1/fCOUNTER).

Note: During HALT mode, input capture is inhibit-

ed (the ARTICRx is never re-loaded) and only the

external interrupt capability can be used.

Note: The ARTICx signal is synchronized on CPU

clock. It takes two rising edges until ARTICRx is

latched with the counter value. Depending on the

prescaler value and the time when the ICAP event

occurs, the value loaded in the ARTICRx register

may be different.

If the counter is clocked with the CPU clock, the

value latched in ARTICRx is always the next coun-

ter value after the event on ARTICx occurred (Fig-

ure 45).

If the counter clock is prescaled, it depends on the

position of the ARTICx event within the counter cy-

cle (Figure 46).

Figure 45. Input Capture Timing Diagram, fcounter = fcpu.

04h

COUNTER

01h

fCOUNTER

xxh

02h

03h

05h

06h

07h

05h

ARTICx PIN

CFx FLAG

ICAP SAMPLED

INTERRUPT

fCPU

ICAP SAMPLED

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