TMS320LF2402A datasheet(63/134 Pages) TI

63 / 134 page

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A

TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A

DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

description of shared I/O pins (continued)

Table 12. Shared Pin Configurations† (Continued)

PIN FUNCTION SELECTED

MUX

CONTROL

MUX CONTROL

I/O PORT DATA AND DIRECTION‡

(MCRx.n = 1)

Primary Function

(MCRX.N = 0)

I/O

CONTROL

(name.bit #)

MUX CONTROL

VALUE AT RESET

(MCRx.n)

DATA BIT NO.§

DIR BIT NO.¶

PORT E

CLKOUT

IOPE0

MCRC.0

PEDATDIR

PWM7

IOPE1

MCRC.1

PEDATDIR

PWM8

IOPE2

MCRC.2

PEDATDIR

PWM9

IOPE3

MCRC.3

PEDATDIR

PWM10

IOPE4

MCRC.4

PEDATDIR

PWM11

IOPE5

MCRC.5

PEDATDIR

PWM12

IOPE6

MCRC.6

PEDATDIR

CAP4/QEP3

IOPE7

MCRC.7

PEDATDIR

PORT F

CAP5/QEP4

IOPF0

MCRC.8

PFDATDIR

CAP6

IOPF1

MCRC.9

PFDATDIR

T3PWM/T3CMP

IOPF2

MCRC.10

PFDATDIR

T4PWM/T4CMP

IOPF3

MCRC.11

PFDATDIR

TDIRB

IOPF4

MCRC.12

PFDATDIR

TCLKINB

IOPF5

MCRC.13

PFDATDIR

† Bold, italicized pin names indicate pin functions at reset.

‡ Valid only if the I/O function is selected on the pin

§ If the GPIO pin is configured as an output, these bits can be written to. If the pin is configured as an input, these bits are read from.

¶ If the DIR bit is 0, the GPIO pin functions as an input. For a value of 1, the pin is configured as an output.

# At reset, all LF240xA devices come up with the W/R/IOPC0 pin in W/R mode. On devices that lack an external memory interface (e.g., LF2406A),

W/R mode is not functional and MCRB.0 must be set to a 0 if the IOPC0 pin is to be used. The XMIF Hi-Z control bit (bit 4 of the SCSR2 register)

is reserved in these devices and must be written with a zero.

|| Bits 15 through 9 of the MCRB register must be written as 1 only. Writing a 0 to any of these bits will cause unpredictable operation of the device.

digital I/O control registers

Table 13 lists the registers available in the digital I/O module. As with other 240xA peripherals, these registers

are memory-mapped to the data space.

Table 13. Addresses of Digital I/O Control Registers

ADDRESS

NAME

7090h

MCRA

I/O MUX control register A

7092h

MCRB

I/O mux control register B

7094h

MCRC

I/O mux control register C

7095h

PEDATDIR

I/O port E data and direction register

7096h

PFDATDIR

I/O port F data and direction register

7098h

PADATDIR

I/O port A data and direction register

709Ah

PBDATDIR

I/O port B data and direction register

709Ch

PCDATDIR

I/O port C data and direction register

709Eh

PDDATDIR

I/O port D data and direction register

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