AFE1302

9

SBWS014

DIGITAL-TO-ANALOG CONVERTER

The Digital-to-Analog Converter (DAC) data for the TX

channel is deserialized and written in four 4-bit registers and

coded in two’s complement, as shown in Table VI.

DAC/ADC HEXDATA

ANALOG I/O

1 SIGN BIT

Positive Full-Scale

7FFF

Mid-Scale

0000

Negative Full-Scale

8000

TABLE VI. One Sign Bit.

ANALOG-TO-DIGITAL CONVERTER

The Analog-to-Digital Converter (ADC) data from the RX

channel is stored in four 4-bit registers and coded in two’s

complement, as shown in Table VII.

SCALABLE TIMING

The AFE1302 scales operation with the clock frequency.

All internal filters change frequency with the clock speed so

that the unit can be used at different frequencies just by

changing the clock speed.

For the RX channel, the digital filtering of the delta-sigma

converter scales directly with the clock speed. For the TX

channel, the power spectral density scales directly with the

clock rate. The transformer and external filter need to be

changed for different frequency requirements.

LAYOUT

The analog front-end of an ADSL system has a number of

conflicting requirements. It must accept and deliver digital

outputs at fairly high rates of speed, and convert the line

input to a high precision (14-bit) digital output. Thus, there

are two sections of the AFE1302: the digital section, and the

analog section. The recommended VCXO circuit layout is

shown in Figure 4.

DIGITAL LAYOUT

The power supply for the digital section of the AFE1302 can

range from 3.3V to 5V. This supply should be decoupled to

digital ground with a ceramic 0.1

µF capacitor placed as

digital ground plane should run to and underneath the digital

a wide printed circuit board trace. A digital ground plane

underneath all digital pins is strongly recommended.

ANALOG LAYOUT

The remaining portion of the AFE1302 should be considered

connected to an analog 5V power plane. Both of these planes

should have a low impedance path to the power supply. The

analog power-supply pins should be decoupled to analog

ground with both a 10

µF tantalum capacitor and a 0.1µF

ceramic capacitor. The ceramic capacitors should be placed

as close to the AFE1302 as possible. The placement of the

tantalum capacitor is not as critical, but should be close to

the pin. In each case, the capacitor should be connected

FIGURE 4. VCXO Circuit Layout, Approximately Two Times Actual Size.

Sensitive Points

No Ground/Power Planes

Or Other Traces In This Area

Ground

Plane

To AFE1302 Pin #41

DAC/ADC HEXDATA

ANALOG I/O

2 SIGN BITS

Positive Full-Scale

3FFF

Mid-Scale

0000

Negative Full-Scale

C000

TABLE VII. Two Sign Bits.