DM6381F datasheet(25/40 Pages) ETC

25 / 40 page

DM336P

V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set

Final

Version: DM336P-DS-F02

August 15, 2000

DM6381/82 Pin Description (continued)

Pin No.

Pin Name

I/O

Description

/RESET

Reset Pin Of DSP Chip, low active.

/IRQ0

Interrupt 0 Input

/IRQ1

Interrupt 1 Input

/IRQ2

Interrupt 2 Input

/IRQ3

Interrupt 3 Input

91 - 92

TEST, TEST1

These three pins define the testing mode operation of

DM6381/DM6382 as followed:

When Test=0

Test1

0, PLL output clock is 89.74MHz.

1, PLL output clock is 80.64MHz.

When Test=1:

Reserved for mass production testing mode.

All these 2 pins are pulled low internally.

FR_SP1

I/O

Frame Signal Of Serial Port 1

TD_SP1

Data Output Pin Of Serial Port 1

The serial data is clocked out through this pin according to the rising

edge of SCLK. The MSB is sent immediately after the falling edge of the

FR_SP1 signal.

RD_SP1

Data Input Pin Of The Serial Port 1

The serial data is sampled at the falling edge of the SCLK. The MSB is

coming immediately after the falling of FR_SP1 signal.

SCLK

Reference Clock For Serial Port 1 And Serial Port 2

100

TD_SP2

Data Output Pin Of Serial Port 2

The serial data is clocked out through this pin according to the rising

edge of SCLK. The MSB is sent immediately after the falling edge of the

FR_SP2 signal.

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