ICS8624 datasheet(9/16 Pages) ICST

9 / 16 page

8624BY

www.icst.com/products/hiperclocks.html

REV. C JUNE 15, 2004

Integrated

Circuit

Systems, Inc.

ICS8624

LOW SKEW, 1-TO-5

DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER

FIGURE 4A. ICS8624 HSTL ZERO DELAY BUFFER SCHEMATIC EXAMPLE

LAYOUT GUIDELINE

The schematic of the ICS8624 layout example is shown in

Figure 4A. The ICS8624 recommended PCB board layout for

this example is shown in

Figure 4B. This layout example is

used as a general guideline. The layout in the actual system

C11

0.01u

(U1-16)

CLK_SEL

(U1-17)

Zo = 50 Ohm

SEL1

(U1-32)

R4A

DIV_SEL[1:0] = 01

VDD

0.1uF

Zo = 50 Ohm

VDD=3.3V

CLK_SEL

R4B

0.1uF

RU5

VDDO=1.8V

SEL1

0.1uF

VDDA

R2A

0.1uF

RU3

(U1-25)

(155.5 MHz)

VDD

R10

Zo = 50 Ohm

RD2

C16

10u

SP = Space (i.e. not intstalled)

R2B

Zo = 50 Ohm

Bypass capacitor located near the power pins

VDDO

RD4

155.5 MHz

SEL0

0.1uF

PLL_SEL

3.3V

RU4

VDD

LVHSTL_input

VDD

(U1-24)

SEL0

RD5

8624

SEL0

SEL1

CLK0

nCLK0

CLK1

nCLK2

CLK_SEL

VDDO

nQ1

nQ2

nQ3

VDDO

RU2

RD3

(U1-9)

3.3V PECL Driver

0.1uF

will depend on the selected component types, the density of

the components, the density of the traces, and the stack up

of the P.C. board.

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