PC87382 datasheet(44/72 Pages) NSC

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Revision 1.2

6.0

Docking LPC Switch

6.1

OVERVIEW

The Docking LPC Switch connects between the main platform LPC bus and the Docking Station LPC bus.

Features:

• Low switch resistance

• LDRQ output sharing between local and Docking DMA requests

• Docking LPC Device Reset control

• Programmable Clock to Reset Delay

• Prevents signal bouncing when the Docking Station is switched on

6.2

FUNCTIONAL DESCRIPTION

6.2.1

Basic Functionality

The Docking LPC Bus signals are divided into the following groups:

Immediate connection signals (DLCLK, DSERIRQ, DCLKRUN): These signals are connected via a low-resistance

switch to the main LPC bus.

Delayed connection signals (DLAD3-0, DLFRAME): These signals are connected via a low-resistance switch to the

main LPC bus. When enabled, the connection is established on LPC Idle detection following CLK2RST Timer expira-

tion.

DLRESET: Driven low starting from the time the switch is enabled until CLK2RST Timer expiration. After CLK2RST

Timer expiration, DLRESET reﬂects the LRESET pin value.

DCLKOUT: When the switch is enabled, DCLKOUT drives the Clock Generator output or clock from CLKIN input (de-

pending on bit 6 of CLOCKCF register; see Section 3.7.6 on page 29) to the Docking device. Otherwise, this pin is

not driven and is held high by an internal pull-up resistor.

DLDRQ: Combined with an internal DMA request on LDRQ output; see Section 6.2.2 on page 44.

The switch connection procedure is triggered by the following condition:

Bit 0 of DLCTL register is written with 1.

Following the switch trigger detection, the following sequence is performed as follows:

1. DLCLK, DSERIRQ, DCLKRUN signals are connected to LCLK, SERIRQ, CLKRUN signals, respectively. DCLKOUT out-

put driver is enabled. DLRESET output is held low (active). CLK2RST timer starts counting.

2. EXP bit of DLCTL register is set on CLK2RST counter reaching the value defined by CLK2RSTVAL field of DLCTL reg-

ister.

3. Host software must poll for the EXP bit. The switch connection is performed when the EXP bit is read with 1. In addition,

the Serial IRQ must be configured to Continuous mode during the switch activation.

4. DLRESET output is deactivated. DLFRAME and DLAD3-0 signals are connected to LFRAME and LAD3-0 signals, re-

spectively. LDRQ sharing mechanism is enabled; see Section 6.2.2.

All Docking LPC signals are held high by internal pull-up resistors while the corresponding switch is in open (disconnected)

state, except DLRESET, which is held low by pull-down resistor.

At VDD Power-up the switch is in disconnected state. Note that the switch state is not affected by the warm reset.

6.2.2

LDRQ Sharing Mechanism

The Docking Station DMA Request DLDRQ and the PC87382 internal DMA Request are combined on LDRQ output using

the LDRQ sharing mechanism. The mechanism performs arbitration between the two DMA Requests.

PC87382 Datenblatt(PDF) 44 Page - National Semiconductor (TI)

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