Datenblatt-Suchmaschine für elektronische Bauteile
  German  ▼
ALLDATASHEETDE.COM

X  

ST92185B Datenblatt(PDF) 61 Page - STMicroelectronics

Teilenummer ST92185B
Bauteilbeschribung  16K/24K/32K ROM HCMOS MCU WITH ON-SCREEN-DISPLAY
PDF  178 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Hersteller  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST92185B Datenblatt(HTML) 61 Page - STMicroelectronics

Back Button ST92185B Datasheet HTML 57Page - STMicroelectronics ST92185B Datasheet HTML 58Page - STMicroelectronics ST92185B Datasheet HTML 59Page - STMicroelectronics ST92185B Datasheet HTML 60Page - STMicroelectronics ST92185B Datasheet HTML 61Page - STMicroelectronics ST92185B Datasheet HTML 62Page - STMicroelectronics ST92185B Datasheet HTML 63Page - STMicroelectronics ST92185B Datasheet HTML 64Page - STMicroelectronics ST92185B Datasheet HTML 65Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 61 / 178 page
background image
61/178
ST92185B - RESET AND CLOCK CONTROL UNIT (RCCU)
4.5 RESET CONTROL UNIT REGISTERS
The RCCU consists of two registers. They are
PCONF and SDRATH. Unless otherwise stated,
unused register bits must be kept in their reset val-
ue in order to avoid problems with the device be-
haviour.
PLL CONFIGURATION REGISTER (PCONF)
R251 - Read/Write
Register Page: 55
Reset value: 0000 0111 (07h)
Bit 7= SRESEN.
Software Reset Enable.
0: RCCU PLL and CSDU are turned off when a
HALT instruction is performed.
1: RCCU will reset the microcontroller when a
HALT instruction is performed.
Bit 6:0= Reserved bits. Leave in their reset state.
CLOCK SLOW DOWN UNIT RATIO REGISTER
(SDRATH)
R254 - Read/Write
Register Page: 55
Reset value:
0010 0xxx (2xh) after software reset
0100 0xxx (4xh) after watchdog reset
0000 0000 (00h) after external reset
Bit 7 = Reserved bit. Leave in its reset state.
Bit 6 = WDGRES.
Watchdog Reset. WDGRES is
automatically set if the last reset was a watchdog
Reset. This is a read only bit.
Bit 5 = SFTRES.
Software Reset. SFTRES is au-
tomatically set if the last reset was a software Re-
set. This is a read only bit.
Bit 4:0 = Reserved bits. Please leave in their reset
state.
70
SRESEN
0
0
0
0
1
1
1
70
0
WDGRES SFTRES
0
0
x
x
x



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datenblatt Download

Go To PDF Page


Link URL



War ALLDATASHEET hilfreich?  [ DONATE ] 

Über Alldatasheet   |   Werbung   |   Kontakt   |   Privatsphäre und Datenschutz   |   Link zum Datenblatt    |   Linktausch   |   Hersteller
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com