AS3843N13 datasheet(13/20 Pages) ETC

13 / 20 page

ASTEC Semiconductor

(2)

(3)

(4)

where f

osc is the oscillator frequency, D is the

maximum duty ratio, V

H is the oscillatorÕs upper

trip point, V

L is the lower trip point, VR is the Ref-

erence voltage, I

D is the discharge current.

Table 1 lists some common values of R

T and the

corresponding maximum duty ratio. To select the

timing components; first, use Table 1 or equation

(2) to determine the value of R

T that will yield the

desired maximum duty ratio. Then, use equation

(1) to calculate the value of C

T. For example, for

a switching frequency of 250 kHz and a maxi-

mum duty ratio of 50%, the value of R

T, from

Table 1, is 683 ½. Applying this value to equation

(1) and solving for C

T gives a value of 4700 pF. In

practice, some fine tuning of the initial values

may be necessary during design. However, due

to the advanced design of the AS3842 oscillator,

once the final values are determined, they will

yield repeatable results, thus eliminating the

need for additional trimming of the timing compo-

nents during manufacturing.

1.3.2 Oscillator enhancements

The AS3842 oscillator is trimmed to provide

guaranteed duty ratio clamping. This means that

the discharge current (I

D ) is trimmed to a value

that compensates for all of the tolerances within

the device (such as the tolerances of V

REG, prop-

agation delays, the oscillator trip points, etc.)

which have an effect on the frequency and max-

imum duty ratio. For example, if the combined

tolerances of a particular device are 0.5% above

nominal, then I

D is trimmed to 0.5% above nomi-

nal. This method of trimming virtually eliminates

the need to trim external oscillator components

during power supply manufacturing. Standard

3842 devices specify or trim only for a specific

value of discharge current. This makes precise

AS384x

Current Mode Controller

Table 1. R

T vs Maximum Duty Ratio

T (½)

Dmax

470

22%

560

37%

683

50%

750

54%

820

58%

910

63%

1,000

66%

1,200

72%

1,500

77%

1,800

81%

2,200

85%

2,700

88%

3,300

90%

3,900

91%

4,700

93%

5,600

94%

6,800

95%

8,200

96%

10,000

97%

18,000

98%

REG

(KL) D

1ÐD

Ð (KH) D

1ÐD

(KL) D

Ð (KH) D

REG

−

≈

0.432

(

REG

−

≈

REG

0.736

−

1ÐD

582 ¥

(0.432)

(0.736)

−

(0.432)

(0.736)

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