05 | Keysight | U5303A PCIe High-Speed Digitizer with On-Board Processing - Data Sheet

Firmware Options

The U5303A PCIe high-speed digitizer provides several firmware

options:

– INT: Interleaved channel sampling functionality

– DDC: Wideband real-time digital down-conversion

Table 1. Firmware options versus sampling rate.

Sampling rate

Firmware

-SR0

-SR1

-SR2

-DGT

-INT

-FDK

-AVG

–

-PKD

–

-TSR

–

-CSR

–

-DDC

–

1. Not available with SS1 and BB1 options.

2. A calibration digitizer function is available with each firmware.

3. Only available with DGT option.

4. On the Virtex-6 LX195ST DPU FPGA.

5. Excepted for 8 first triggers.

INT interleaved channel sampling functionality

This interleave option allows two channels to be combined and to

reach 3.2 GS/s (SR2 option) in one channel acquisition mode.

FDK custom firmware capability

U5340A FPGA development kit.

AVG firmware for real-time sampling and averaging

Averaging signals reduces random noise effects, improving

the signal-to-noise ratio, as well as increasing resolution and

dynamic range.

Synchronous real-time sampling and accumulation up to

3.2 GS/s on single-channel and dual-channel with:

– Accumulation of 1 up to 520,000 triggers in steps of

– Effective acquisition length of up to 480 kSamples in single

channel or 240 kSamples per channel in dual-channel.

– Noise suppressed accumulation (NSA).

– Self-trigger mode for minimal synchronous noise.

– Baseline stabilization algorithm and digital offset.

PKD firmware for real-time signal peak detection

The peak detection firmware allows real-time acquisition and

peak detection with the possibility to generate a histogram of

peak versus time for successive acquisitions.

Synchronous real-time sampling and peak detection up to

3.2 GS/s on single-channel and dual-channel with:

– Accumulation of 1 up to 520,000 triggers in steps of

– Effective acquisition length of up to 480 kSamples in single

channel or 240 kSamples per channel in dual-channel.

– Self-trigger mode for minimal synchronous noise.

– Baseline stabilization algorithm and digital offset.

Easy firmware switch

A simple call to the configuration function will enable to switch to

the required option.

DGT digitizer firmware

The digitizer firmware:

– Allows standard data acquisition, including: digitizer

initialization, setting of the acquisition and clocking modes,

management of channel triggering for best synchronization,

storing data in the internal memory and/or transferring them

through the backplane bus.

– Implements multi-record acquisition functionality.

– Supports fixed internal clocking frequency with internal or

external reference, and variable frequency external clock.

– Programmable binary decimation available with SR1 and SR2

defined in the range of 1 to 10 for single record.

e.g. for a U5303A-SR2 you can select from 3.2 GS/s (with

interleaving) down to 3.125 MS/s.

– Trigger time interpolator (TTI): high precision integrated

time to digital converter can be used to increase time

measurement accuracy.