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NERO-LP1 Datenblatt(PDF) 9 Page - Future Technology Devices International Ltd. |
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NERO-LP1 Datenblatt(HTML) 9 Page - Future Technology Devices International Ltd. |
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9 / 18 page ![]() Copyright © 2016 Future Technology Devices International Limited 9 NerO Module Datasheet Version 1.0 Doc ument Reference N o.: FT _001285 C learance N o.: FT DI#4 85 Pin No Pin Name Description 1 SCL I2C Serial Bus, clock line 2 SDA I2C Serial Bus, data line 3 AREF Analog Reference pin for ADC 4 GND Ground 5 13 GPIO 13 6 12 GPIO 12 7 11 GPIO 11/ PWM 8 10 GPIO 10/ PWM 9 9 GPIO 9/ PWM 10 8 GPIO 8 Table 3 - Pin Mapping of CN5 Table 4 - Pin Mapping of CN7lists the entire pin mapping on CN7 Pin No Pin Name Description 1 7 GPIO 7 2 6 GPIO 6/ PWM 3 5 GPIO 5/ PWM 4 4 GPIO 4 5 3 GPIO 3/ PWM 6 2 GPIO 2 7 1 GPIO 1 8 0 GPIO 0 Table 4 - Pin Mapping of CN7 Table 5 - Pin Mapping of CN6 lists the entire pin mapping on CN6 Pin No Pin Name Description 1 A5 Analog input 5 2 A4 Analog input 4 3 A3 Analog input 3 4 A2 Analog input 2 5 A1 Analog input 1 6 A0 Analog input 0 Table 5 - Pin Mapping of CN6 |
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