AUIRF2804 datasheet(2/13 Pages) INFINEON

2 / 13 page

AUIRF2804/S/L

2015-9-30

Notes:





Calculated continuous current based on maximum allowable junction temperature. Bond wire current limit is 195A.

Note that current limitations arising from heating of the device leads may occur with some lead mounting arrangements.

(Refer to AN-1140)



Repetitive rating; pulse width limited by max. junction temperature. (See fig. 11)



Limited by TJmax, starting TJ = 25°C, L = 0.24mH, RG = 25, IAS = 75A, VGS =10V. Part not recommended for use above this value.



Pulse width

1.0ms; duty cycle  2%.



Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS.



This value determined from sample failure population, starting TJ = 25°C, L = 0.24mH, RG = 25, IAS = 75A, VGS =10V.



This is applied to D2Pak When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and

soldering techniques refer to application note #AN-994



Max RDS(on) for D

2Pak and TO-262 (SMD) devices.



TO-220 device will have an Rth value of 0.45°C/W.



All AC and DC test condition based on old Package limitation current = 75A.

Static @ TJ = 25°C (unless otherwise specified)

Parameter

Min. Typ. Max. Units

Conditions

V(BR)DSS

Drain-to-Source Breakdown Voltage

–––

VGS = 0V, ID = 250µA

V(BR)DSS/TJ

Breakdown Voltage Temp. Coefficient

––– 0.031 –––

V/°C Reference to 25°C, ID = 1mA

RDS(on) SMD

Static Drain-to-Source On-Resistance

–––

1.5

2.0

VGS = 10V, ID = 75A 

RDS(on) TO-220 Static Drain-to-Source On-Resistance

–––

1.8

2.3

VGS = 10V, ID = 75A 

VGS(th)

Gate Threshold Voltage

2.0

–––

4.0

VDS = VGS, ID = 250µA

gfs

Forward Trans conductance

130

–––

VDS = 10V, ID = 75A

IDSS

Drain-to-Source Leakage Current

–––

µA

VDS =40 V, VGS = 0V

–––

250

VDS =40V,VGS = 0V,TJ =125°C

IGSS

Gate-to-Source Forward Leakage

–––

200

VGS = 20V

Gate-to-Source Reverse Leakage

–––

-200

VGS = -20V

Dynamic Electrical Characteristics @ TJ = 25°C (unless otherwise specified)

Total Gate Charge

–––

160

240

ID = 75A

Qgs

Gate-to-Source Charge

–––

VDS = 32V

Qgd

Gate-to-Drain Charge

–––

VGS = 10V

td(on)

Turn-On Delay Time

–––

VDD = 20V

Rise Time

–––

120

–––

ID = 75A

td(off)

Turn-Off Delay Time

–––

130

–––

RG= 2.5

Fall Time

–––

130

–––

VGS = 10V 

Internal Drain Inductance

–––

4.5

–––

Between lead,

6mm (0.25in.)

Internal Source Inductance

–––

7.5

–––

from package

and center of die contact

Ciss

Input Capacitance

–––

6450 –––

VGS = 0V

Coss

Output Capacitance

–––

1690 –––

VDS = 25V

Crss

Reverse Transfer Capacitance

–––

840

–––

ƒ = 1.0MHz, See Fig. 5

Coss

Output Capacitance

–––

5350 –––

VGS = 0V, VDS = 1.0V ƒ = 1.0MHz

Coss

Output Capacitance

–––

1520 –––

VGS = 0V, VDS = 32V ƒ = 1.0MHz

Coss eff.

Effective Output Capacitance

–––

2210 –––

VGS = 0V, VDS = 0V to 32V 

Diode Characteristics

Parameter

Min. Typ. Max. Units

Conditions

Continuous Source Current

–––

––– 270

MOSFET symbol

(Body Diode)

showing the

ISM

Pulsed Source Current

–––

––– 1080

integral reverse

(Body Diode)

p-n junction diode.

VSD

Diode Forward Voltage

–––

1.3

TJ = 25°C,IS = 75A,VGS = 0V 

trr

Reverse Recovery Time

–––

ns TJ = 25°C ,IF = 75A, VDD = 20V

Qrr

Reverse Recovery Charge

–––

100

di/dt = 100A/µs 

ton

Forward Turn-On Time

Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)



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