PI2126

Rev 1.1

Layout Recommendation:

Use the following general guidelines when designing

printed circuit boards. An example of the typical land

pattern for the PI2126 is shown in Figure 20:



Make sure to have a solid ground (return) plane to

reduce circuit parasitic inductance.



Connect all S pads together with a wide trace to

reduce trace parasitics to accommodate the high

current input, and also connect all D pads together

with a wide trace to accommodate the high current

output.



Connect the SP pin to the S pins and connect the SN

pin to D pins outside the SiP as shown in Figure 20.



Use 1oz copper or thicker if possible to reduce trace

resistance and power dissipation.



C6 typically is not required, but if addition bypassing is

preferred, Figure 20 shows the appropriate layout for

an extra VC capacitor.

Figure 20: Layout recommendation

SP

SN

S

D

D

D

D

S

S

Vin

Vout

PI2126

D

D

D

D

S

S

S

S

S

VR

FT

Figure 21: PI2126 Mounted on PI2126-EVAL1

Please visit http://vicorpower.com/picorpower/ for information on PI2122-EVAL1

EOL