2-OUTPUT 3.3V PCIE CLOCK GENERATOR

4

OCTOBER 18, 2016

9FGL02 DATASHEET

Test Loads

Alternate Terminations

The 9FGL family can easily drive LVPECL, LVDS, and CML logic. See “AN-891 Driving LVPECL, LVDS, and CML Logic with

IDT's "Universal" Low-Power HCSL Outputs” for details.

REF Output

33

REF Output Test Load

5pF

Zo = 50 ohms

Rs

Rs

Low-Power Differential Output Test Load

2pF

2pF

5 inches

Zo=100ohm

Note: The device can drive transmission line lengths greater

than those specified by the PCIe SIG

Terminations

Device

Zo (Ω)Rs (Ω)

9FGL0241

100

None needed

9FGL0251

100

7.5

9FGL02P1

100

Prog.

9FGL0241

85

N/A

9FGL0251

85

None needed

9FGL02P1

85

Prog.