LM2647 datasheet(13/25 Pages) NSC

13 / 25 page

Operation Descriptions (Continued)

goes to zero (and stays there). Though not displayed, Power

Good also goes low within less than 100ns of the EN pin

going low (

∆t

SD, see Electrical Characteristics table). There-

fore in this case, the controller is NOT waiting for the output

to actually fall out of the Power Good window before it

signals Power Not Good. Note that since there is a constant

current 2A load applied at the output, the stored charge on

the output capacitor continues to be discharged into the

load. From

∆V/∆t=i/C=2A/330µF it can be seen that the

output voltage (say 1V) will fall to zero in about 165µs, as will

be observed.

But if the load is very close to zero, the only means for the

output capacitor to discharge is through the resistive divider

on the feedback pin (if any) and any internal bleeder resistor

present. In fact there is such an internal bleeder resistor in

the LM2647 and it performs Soft-shutdown by discharging

the output capacitors gradually. Its value is about 20

Ω and it

is internally connected between the SENSE pin and ground

whenever the EN pin is taken low. Note that this will be

perceivable only when the external load is small, and pro-

vided a normal shutdown is being carried out. Normal shut-

down as being defined here calls for the Enable pin to be the

cause of the outputs being disabled. In a shutdown provoked

by a fault, the situation is very different as will be explained

later.

POWER GOOD/NOT GOOD SIGNALING

PGOOD is an open-Drain output pin with an external pull-up

resistor connected to 5V. It goes high (non-conducting) when

both the outputs are within the regulation band as deter-

mined by the Power Good window detector stage on the

feedback pin (see Block Diagram). PGOOD goes low (con-

ducting) when either of the two outputs falls out of this

window. This signal is referred to as Power Not Good here.

A glitch filter of 7µs filters out noise, and helps prevent

spurious PGOOD responses. So Power Not Good is not

asserted until 7µs after either of the two outputs have fallen

out of the Power Good window (see

∆t

PG_NOK in Electrical

Characteristics table). With the feedback pin voltage rising

towards regulation value, there is a 20µs delay between both

the outputs being in regulation and the signaling of Power

Good (see

∆t

PG_OK

in Electrical Characteristics table).

Power Not Good is signaled within 100ns of the Enable pin

being pulled low (see

∆t

in Electrical Characteristics

table), irrespective of the fact that the outputs could still be in

regulation. The Soft-start capacitor is also then discharged

as explained earlier.

VIN POWER-OFF

The LM2647 has an internal comparator that also looks at

VIN. If VIN falls to about 4.5V (roughly), switching ceases.

The response is slightly different under FPWM or SKIP

modes, but the final result is the same. In both cases ulti-

mately, LDRV is latched high and so the output capacitors

are discharged through the lower FETs. Power Not Good

has meanwhile already been signaled and a fault condition is

asserted shortly thereafter.

In Figure 7 and Figure 8 the situation where the connection

to the input DC power source is abruptly removed is shown

for two cases.

In the first case (FPWM mode, Figure 7), LDRV goes high

immediately, as soon as VIN falls to about 4.5V. For the

second case (SKIP mode, Figure 8), the output starts to

discharge into the load resistor. Then Power Not Good is

signaled. Finally, when the output falls below the Under-

voltage threshold a fault condition is asserted. This is ac-

companied by LDRV latching high. The output then suddenly

collapses just as it does for FPWM mode. Note that once

VIN reaches 4.5V, it does not fall quickly thereafter. The

reason is that there is no applied external voltage dragging it

low (in our case as it is described), nor is there any signifi-

cant consumption from the VIN rail since the converter has

stopped switching.

20056314

CH1: LDRV, CH2: Vo, CH3: SW, CH4: IL (1A/div)

Output 1V @ 2A, VIN = 10V, FPWM/SKIP, L = 10µH, f = 300kHz, COUT =

330µF

FIGURE 6. Shutdown

20056315

CH1: PGOOD, CH2: VIN, CH3: LDRV, CH4: Vo

Output 1V @ 0.02A, VIN = 9.75V, FPWM, L = 10µH, f = 300kHz, COUT =

660µF

FIGURE 7. VIN Removal in FPWM Mode

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