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SST26VF032BA Datenblatt(PDF) 27 Page - Microchip Technology |
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SST26VF032BA Datenblatt(HTML) 27 Page - Microchip Technology |
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27 / 77 page ![]() 2013-2016 Microchip Technology Inc. DS20005218E-page 27 SST26VF032B / SST26VF032BA 5.19 Chip-Erase The Chip-Erase instruction clears all bits in the device to ‘1.’ The Chip-Erase instruction is ignored if any of the memory area is protected. Prior to any write operation, execute the WREN instruction. To execute a Chip-Erase operation, the host drives CE# low, sends the Chip-Erase command cycle (C7H), then drives CE# high. Poll the BUSY bit in the Status register, or wait TSCE, for the completion of the internal, self-timed, Write operation. See Figures 5-23 and 5-24 for the Chip Erase sequence. FIGURE 5-23: CHIP-ERASE SEQUENCE (SQI) FIGURE 5-24: CHIP-ERASE SEQUENCE (SPI) 20005218 F09.1 MODE 3 0 1 SCK SIO(3:0) CE# C1 C0 MODE 0 Note: C[1:0] = C7H CE# SO SI SCK 01 2 3 4 5 6 7 C7 HIGH IMPEDANCE MODE 0 MODE 3 20005218 F59.0 MSB |
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