CS86 Series

2

(Continued)

• Output buffer cells with noise reduction circuits

• Input buffer cells and bidirectional buffer cells with on-chip input pull-up/pull-down resistors

• Buffer cells for crystal oscillation circuits

• Special interfaces : SSTL2, PCI, P-CML, T-LVTTL, USB 2.0, IEEE1394, and others.

• IP macros

: CPU (ARM9, FR-V, and others) , DSP, PCI, IEEE1394, USB 2.0, IrDA, PLL, DAC, ADC,

and others.

• Capable of incorporating compiled cells (RAM/ROM/Register file/Delay line)

• Configurable internal bus circuits

• Advanced hardware/software co-design environment

• Short-term development using Physical Synthesis tool

• Low power consumption using Low Power Synthesis tool

• Short-term development using a timing driven layout tool

• Hierarchical design environment for supporting large-scale circuits

• Support for Signal-Integrity

• Support for Memory (RAM, ROM) SCAN

• Support for Memory (RAM) BIST

• Support for Boundary SCAN

• Support for path delay test

• A variety of package options : QFP, TQFP, LQFP, HQFP, PBGA, FBGA, FLGA, EBGA