SK10E151PJ datasheet(1/5 Pages) SEMTECH

Teilenummer	SK10E151PJ

Bauteilbeschribung	6-bit D register

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Revision 1/.ebruary 13, 2001

SK10/100E151

6-Bit D Register

Description

.eatures

.unctional Block Diagram

PIN Description

The SK10/100E151 offers 6 edge-triggered, high-speed,

master-slave D-type flip-flops with differential outputs,

designed for use in new high-performance ECL systems.

This device is fully compatible with MC10E151 and

MC100E151. The two external clock signals (CLK1, CLK2)

are gated through a logical OR operation before use as

clocking control for the flip-flops. Data is clocked into

the flip-flops on the rising edge of either CLK1 or CLK2

(or both).

When both CLK1 and CLK2 are at a logic

LOW, data enters the master and is transferred to the

slave when either CLK or CLK2 (or both) go HIGH.

The MR (Master Reset) signal operates asynchronously

to make all Q outputs go to a logic LOW.

•

1100 MHz Toggle Frequency

•

Extended 100E VEE Range of –4.2V to –5.46V

•

Differential Outputs

•

Asynchronous Master Reset

•

Dual Clocks

•

Internal 75K

Ω Input Pull-Down Resistors

•

ESD Protection of >4000V

•

Fully Compatible with MC10E/100E151

•

Specified Over Industrial Temperature Range:

–40oC to +85oC

•

Available in 28-Pin PLCC Package

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Qs

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D

Q0

D0

Q0*

R

D

Q1

D1

Q1*

R

D

Q2

D2

Q2*

R

D

Q3

D3

Q3*

R

D

Q4

D4

Q4*

R

D

Q5

D5

CLK1

CLK2

MR

Q5*

R

26

27

28

1

2

3

4

18

17

16

15

14

13

12

Q4*

Q4

VCC

Q3*

Q3

Q2*

Q2

D5

D4

D3

VEE

D2

D1

D0

PLCC

TOP VIEW

Ähnliche Beschreibung - SK10E151PJ

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