WM8281ECSSLASHR datasheet(263/392 Pages) CIRRUS

263 / 392 page

WM8281

Rev 4.0

263

There are some restrictions to be observed regarding the sample rate control configuration, as noted

below:



The input (ADC / Digital Microphone) and output (DAC) signal paths must always be

associated with the SYSCLK clocking domain.



All external clock references (MCLK input or Slave mode AIF input) must be within 1% of

the applicable register setting(s).



The input (ADC / DMIC) sample rate is valid from 8kHz to 192kHz. If 768kHz DMIC clock

rate is selected, then the supported sample rate is valid from 8kHz to 16kHz only.



The output (DAC) sample rate is valid from 8kHz to 192kHz.



The Mic Mute mixer sample rate is valid from 8kHz to 192kHz.



The Effects (EQ, DRC, LHPF) sample rate is valid from 8kHz to 192kHz. When the DRC is

enabled, the maximum sample rate for these functions is 96kHz.



The Tone Generator sample rate is valid from 8kHz to 192kHz.



The Haptic Signal Generator sample rate is valid from 8kHz to 192kHz.



The Asynchronous Sample Rate Converter (ASRC) supports sample rates 8kHz to 48kHz.

The associated SYSCLK and ASYNCLK sample rates must both be 8kHz to 48kHz.



The Isochronous Sample Rate Converters (ISRCs) support sample rates 8kHz to 192kHz.

For each ISRC, the higher sample rate must be an integer multiple of the lower rate.

AUTOMATIC SAMPLE RATE DETECTION

The WM8281 supports automatic sample rate detection on the digital audio interfaces (AIF1, AIF2

and AIF3). Note that this is only possible when the respective interface is operating in Slave mode (ie.

when LRCLK and BCLK are inputs to the WM8281).

Automatic sample rate detection is enabled using the RATE_EST_ENA register bit. The LRCLK input

pin selected for sample rate detection is set using the LRCLK_SRC register.

Up to four audio sample rates can be configured for automatic detection; these sample rates are

selected using the SAMPLE_RATE_DETECT_n registers. Note that the function will only detect

sample rates that match one of the SAMPLE_RATE_DETECT_n registers.

If one of the selected audio sample rates is detected on the selected LRCLK input, then a Control

Write Sequence will be triggered. A unique sequence of actions may be programmed for each of the

detected sample rates. Note that the applicable control sequences must be programmed by the user

for each detection outcome. See “Control Write Sequencer” for further details.

The TRIG_ON_STARTUP register controls whether the sample rate detection circuit responds to the

initial detection of the applicable interface (ie. when the AIFn interface starts up).

When TRIG_ON_STARTUP=0, then the detection circuit will only respond (ie. trigger the Control

Write Sequencer) to a change in the detected sample rate - the initial sample rate detection will be

ignored.

(Note that the ‘initial sample rate detection’ is the first detection of a sample rate that matches

one of the SAMPLE_RATE_DETECT_n registers.)

When TRIG_ON_STARTUP=1, then the detection circuit will trigger the Control Write Sequencer

whenever a selected sample rate is detected, including when the AIF interface starts up, or when the

sample rate detection is first enabled.

As described above, setting TRIG_ON_STARTUP=0 is designed to inhibit any response to the initial

detection of a sample rate that matches one of the SAMPLE_RATE_DETECT_n registers. Note that,

if the LRCLK_SRC setting is changed, or if the detection function is disabled and re-enabled, then a

subsequent detection of a matching sample rate may trigger the Control Write Sequencer, regardless

of the TRIG_ON_STARTUP setting.

WM8281ECS/R Datenblatt(PDF) 263 Page - Cirrus Logic

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