WM8281ECSSLASHR datasheet(267/392 Pages) CIRRUS

267 / 392 page

WM8281

Rev 4.0

267

MISCELLANEOUS CLOCK CONTROLS

The WM8281 requires a 32kHz clock for miscellaneous de-bounce functions. This can be generated

automatically from SYSCLK, or may be input directly as MCLK1 or MCLK2. The 32kHz clock source

is selected using the CLK_32K_SRC register. The 32kHz clock is enabled using the CLK_32K_ENA

The 32kHz clock can be maintained in Sleep mode, if required for de-bouncing any of the configured

Wake-Up signals (eg. JACKDET or GPIO5). Note that the 32kHz clock must be derived from the

MCLK2 pin in this case (CLK_32K_SRC=01). See “Low Power Sleep Configuration” for more details

of the Sleep mode.

A clock output (OPCLK) derived from SYSCLK can be output on a GPIO pin. See

“General Purpose

Input / Output

” to configure a GPIO pin for this function.

A clock output (OPCLK_ASYNC) derived from ASYNCCLK can be output on a GPIO pin. See

“General Purpose Input / Output” to configure a GPIO pin for this function.

The WM8281 provides integrated pull-down resistors on the MCLK1 and MCLK2 pins. This provides a

flexible capability for interfacing with other devices.

The clocking scheme for the WM8281 is illustrated in Figure 69.

WM8281ECS/R Datenblatt(PDF) 267 Page - Cirrus Logic