WM8281ECSSLASHR datasheet(307/392 Pages) CIRRUS

307 / 392 page

WM8281

Rev 4.0

307

LDO1 REGULATOR AND DCVDD SUPPLY

The LDO1 voltage regulator is intended for generating the DCVDD domain, which powers the digital

core functions on the WM8281. In this configuration, the LDO output (LDOVOUT) should be

connected to the DCVDD pin. Note that the use of the LDO1 regulator to power external circuits

cannot be supported by the WM8281.

LDO1 is powered by LDOVDD and can be controlled using hardware or software controls. Note that,

depending on the application requirements, it may be necessary to use both the hardware and

software enables for LDO1, as described below.

Under hardware control, LDO1 is enabled when a

logic ‘1’ is applied to the LDOENA pin. The logic

level is determined with respect to the DBVDD1 voltage domain. LDO1 is also enabled when the

LDO1_ENA software control register is set to 1. Note that, to disable LDO1, the hardware and

software controls must both be de-asserted.

When LDO1 is enabled, the LDOVOUT voltage can be selected using the LDO1_VSEL control field.

Note that the default output voltage should always be used for normal operation. For correct Sleep

mode behaviour, the LDOVOUT voltage should be reduced to 1.175V immediately before entering

Sleep mode. See Table 125 for

further details. See also “Low Power Sleep Configuration”.

When LDO1 is disabled, the LDOVOUT pin can be configured to be floating or to be actively

discharged. This is selected using the LDO1_DISCH register bit.

It is possible to supply DCVDD from an external supply. In this configuration, the LDOVOUT pin

should be left floating; it must not be connected to the DCVDD pin. The LDO1 regulator is not used in

this case, and must be disabled at all times.

For recommended use of the Sleep / Wake-

Up functions (see “Low Power Sleep Configuration”), it is

assumed that DCVDD is powered from the output of LDO1. In this case, Sleep mode is selected when

LDO1 is disabled, causing the DCVDD supply to be removed. Note that the AVDD, DBVDD1, and

LDOVDD supplies must be present throughout the Sleep mode duration.

If DCVDD is powered externally (not from LDO1), then the ISOLATE_DCVDD1 register bit must be

controlled as described in Table 125 when selecting WM8281 Sleep mode. In this case, Sleep mode

is selected by setting the ISOLATE_DCVDD1 register bit, and then removing the DCVDD supply. For

applications where DCVDD is powered externally, only the AVDD and DBVDD1 supplies are required

in Sleep mode.

An internal pull-down resistor is enabled by default on the LDOENA pin. This is configurable using the

LDO1ENA_PD register bit. A pull-up resistor is also available, as described in Table 125. When the

pull-up and pull-down resistors are both enabled, the WM8281

provides a ‘bus keeper’ function on the

LDOENA pin. The bus keeper function holds the input logic level unchanged whenever the external

circuit removes the drive (eg. if the signal is tri-stated).

If DCVDD

is powered from LDO1, then a logic ‘1’ must be applied to the LDOENA pin during power-

up, to enable LDO1. The LDO must also be enabled using the LDOENA pin following a Hardware

Reset or Software Reset, to allow the device to re-start. (It is recommended that the LDOENA pin is

asserted before any reset, and is held at logic ‘1’ until after the reset is complete; this ensures the

DSP firmware memory contents can be retained, and also allows faster reset time.)

For normal operation following Power-On Reset (POR), Hardware Reset, or Software Reset, LDO1

must be enabled using the hardware or software controls described above. Note that when the

LDO1_ENA bit is set to 1, the LDOENA pin has no effect and may be de-asserted - the LDO is then

under software control, allowing Sleep mode to be selected under register control, including via the

Control Write Sequencer.

See “Power-On Reset (POR)” and “Hardware Reset, Software Reset, Wake-Up, and Device ID” for

details of WM8281

Resets. See also “Low Power Sleep Configuration” for details of the Sleep / Wake-

up functions.

The LDO1 Regulator circuit is illustrated in Figure 82. The associated register control bits are

described in Table 125.

Note that the LDO output requires an external decoupling capacitor; this requirement is typically

achieved via decoupling on the DCVDD pins. Refer to the

“Applications Information” section for

recommended external components.

WM8281ECS/R Datenblatt(PDF) 307 Page - Cirrus Logic

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